ZHCSEL1C May   2012  – Februrary 2016 LM5134

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input-to-Output Logic
        2. 8.2.2.2 Input Threshold Type
        3. 8.2.2.3 VDD Bias Supply Voltage
        4. 8.2.2.4 Peak Source and Sink Currents
        5. 8.2.2.5 Enable and Disable Function
        6. 8.2.2.6 Propagation Delay
        7. 8.2.2.7 PILOT MOSFET Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

Attention must be given to board layout when using LM5134. Some important considerations include:

  1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and discharge the FETs gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate.
  2. To reduce the loop inductance, the driver should be placed as close as possible to the FETs. The gate trace to and from the FETs are recommended to be placed closely side by side, or directly on top of one another.
  3. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form a LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp the ringing.

10.2 Layout Example

LM5134 LM5134 Layout example.png Figure 27. LM5134 Layout Example

10.3 Power Dissipation

It is important to keep the power consumption of the driver below the maximum power dissipation limit of the package at the operating temperature. The total power dissipation of the LM5134 is the sum of the gate charge losses and the losses in the driver due to the internal CMOS stages used to buffer the output as well as the power losses associated with the quiescent current.

The gate charge losses include the power MOSFET gate charge losses as well as the PILOT FET gate charge losses and can be calculated as follows:

Equation 2. Pg = (Qgo + Qgp) × VDD × FSW

Or

Equation 3. Pg = (Co + Cp) × VDD2 × FSW

where

  • Fsw is switching frequency
  • Qgo is the total input gate charge of the power MOSFET
  • Qgp is the total input gate charge of the PILOT MOSFET

Co and Cp are the load capacitance at OUT and PILOT outputs respectively. It should be noted that due to the use of an external turnoff switch, part of the gate charge losses are dissipated in the external turnoff switch. Therefore, the actual gate charge losses dissipated in the LM5134 is less than predicted by the above expressions. However, they are a good conservative design estimate.

The power dissipation associated with the internal circuit operation of the driver can be estimated with the characterization curves of the LM5134. For a given ambient temperature, the maximum allowable power losses of the IC can be defined using Equation 4.

Equation 4. P = (TJ – TA) / θJA

where

  • P is the total power dissipation of the driver