ZHCSI53A May   2018  – November 2018 LM5122ZA

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout (UVLO)
      2. 7.3.2  High-Voltage VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Slope Compensation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  PWM Comparator
      7. 7.3.7  Soft Start
      8. 7.3.8  HO and LO Drivers
      9. 7.3.9  Bypass Operation (VOUT = VIN)
      10. 7.3.10 Cycle-by-Cycle Current Limit
      11. 7.3.11 Clock Synchronization
      12. 7.3.12 Maximum Duty Cycle
      13. 7.3.13 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
      2. 7.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)
      3. 7.4.3 Hiccup-Mode Overload Protection
      4. 7.4.4 Slave Mode and SYNCOUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Sub-Harmonic Oscillation
      3. 8.1.3 Interleaved Boost Configuration
      4. 8.1.4 DCR Sensing
      5. 8.1.5 Output Overvoltage Protection
      6. 8.1.6 SEPIC Converter Simplified Schematic
      7. 8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
      8. 8.1.8 Negative to Positive Conversion
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor RT
        2. 8.2.2.2  UVLO Divider RUV2, RUV1
        3. 8.2.2.3  Input Inductor LIN
        4. 8.2.2.4  Current Sense Resistor RS
        5. 8.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 8.2.2.6  Slope Compensation Resistor RSLOPE
        7. 8.2.2.7  Output Capacitor COUT
        8. 8.2.2.8  Input Capacitor CIN
        9. 8.2.2.9  VIN Filter RVIN, CVIN
        10. 8.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 8.2.2.11 VCC Capacitor CVCC
        12. 8.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 8.2.2.13 Soft-Start Capacitor CSS
        14. 8.2.2.14 Restart Capacitor CRES
        15. 8.2.2.15 Low-Side Power Switch QL
        16. 8.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 8.2.2.17 Snubber Components
        18. 8.2.2.18 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.1.3 Interleaved Boost Configuration

Interleaved operation offers many advantages in single output, high current applications such as higher efficiency, lower component stresses and reduced input and output ripple. For dual phase interleaved operation, the output power path is split reducing the input current in each phase by one-half. Ripple currents in the input and output capacitors are reduced significantly since each channel operates 180 degrees out of phase from the other. Shown in Figure 30 is a normalized (IRMS / IOUT) output capacitor ripple current vs duty cycle for both a single phase and dual phase boost converter, where IRMS is the output current ripple RMS.

LM5122ZA Norm Output Capac.pngFigure 30. Normalized Output Capacitor RMS Ripple Current

To configure for dual phase interleaved operation, configure one device as a master and configure the other device in slave mode by connecting FB to VCC. Also connect COMP, UVLO, RES, SS and SYNCOUT on the master side to COMP, UVLO, RES, SS and SYNCIN on slave side, respectively. The compensation network is connected between master FB and the common COMP connection. The output capacitors of the two power stages are connected together at the common output.

LM5122ZA Dual Phased Intrlvd.gifFigure 31. Dual Phase Interleaved Boost Configuration

Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on the master side to the SYNCIN on the slave side.

LM5122ZA Dual Phase Config Tim.gifFigure 32. Dual Phase Configuration and Timing Diagram

Each channel is synchronized by an individual external clock in Figure 33. The SYNCOUT pin is used in Figure 34 requiring only one external clock source. A 50% duty cycle of external synchronization pulse should be always provided with this daisy chain configuration.

Current sharing between phases is achieved by sharing one error amplifier output of the master controller with the 3 slave controllers. Resistor sensing is a preferred method of current sensing to accurately balance the phase currents.

LM5122ZA 4 Phase Timing Diag [a].gifFigure 33. 4-Phase Timing Diagram Individual Clock
LM5122ZA 4 Phase Timing Diag [b].gifFigure 34. 4-Phase Timing Diagram Daisy Chain