SNVS255B May   2004  – September 2016 LM5110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage and Level Shifter
      2. 8.3.2 Output Stage
      3. 8.3.3 Turn-off with Negative Bias
      4. 8.3.4 UVLO and Power Supplies
      5. 8.3.5 Shutdown SHDN
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Parallel Outputs
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Drive Power Requirement Calculations in LM5110
      2. 11.3.2 Continuous Current Rating of LM5110
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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10 Power Supply Recommendations

The recommended bias supply voltage range for LM5110 is from 3.5 V to 14 V. The upper end of this range is driven by the 15 V absolute maximum voltage rating of the VCC. TI recommends keeping proper margin to allow for transient voltage spikes.

A local bypass capacitor must be placed between the VCC and IN_REF pins, as well as between the VCC and VEE. This capacitor must be placed as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors in parallel: a 100-nF ceramic surface-mount capacitor for high frequency filtering placed as close to VCC as possible, and another surface-mount capacitor, 220 nF to 10 µF, for IC bias requirements.