SNVS215D April   2003  – November 2015 LM5030

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Voltage Start-Up Regulator
      2. 7.3.2 Error Amplifier
      3. 7.3.3 PWM Comparator
      4. 7.3.4 Current Limit and Current Sense
      5. 7.3.5 Oscillator, Shutdown and Sync Capability
      6. 7.3.6 Slope Compensation
      7. 7.3.7 Soft Start and Shutdown
      8. 7.3.8 OUT1, OUT2, and Time Delay
      9. 7.3.9 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC
        2. 8.2.2.2 Current Sense
        3. 8.2.2.3 Shutdown
        4. 8.2.2.4 External Sync
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

DGS, DPR Package
10-Pin VSSOP, WSON
Top View
LM5030 20058112.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
COMP 3 O Output to the error amplifier There is an internal 5-kΩ pullup resistor on this pin. The error amplifier provides an active sink.
CS 8 I Current sense input Current sense input for current mode control and current limit sensing. Using separate dedicated comparators, if CS exceeds 0.5 V, the outputs will go into cycle-by-cycle current limit. If CS exceeds 0.625 V the outputs will be disabled and a softstart commenced.
GND 7 — Return Ground
OUT1 5 O Output of the PWM controller Alternating PWM output gate driver
OUT2 6 O Output of the PWM controller Alternating PWM output gate driver
RT 9 I Oscillator timing resistor pin and synchronization input An external resistor sets the oscillator frequency. This pin will also accept synchronization pulses from an external oscillator.
SS 10 I Dual purpose soft start and shutdown pin A 10-µA current source and an external capacitor set the softstart timing length. The controller will enter a low power state if the SS pin is pulled below the typical shutdown threshold of 0.45 V.
VIN 1 I Source input voltage Input to start-up regulator. Input range 14 to 100 V.
VFB 2 I Inverting input to the error amplifier The non-inverting input is internally connected to a 1.25-V reference.
VCC 4 I/O Output from the internal high-voltage series pass regulator. The regulation setpoint is
7.7 V.		 If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal series pass regulator will shutdown, reducing the IC power dissipation.
WSON
DAP		 SUB — Die substrate The exposed die attach pad on the WSON package should be connected to a PCB thermal pad at ground potential. For additional information on using TI's No Pull Back WSON package, refer to WSON Application Note AN-1187 (SNOA401).