SNAS276G Data sheet | 德州仪器 TI.com.cn

SNAS276G May 2005 – September 2015 LM4550B

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PT|48
- MTQF003C

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6 Pin Configuration and Functions

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48-Pin LQFP

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Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
PC_BEEP	12	I	Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level can be muted or adjusted from 0 dB to –45 dB in 3-dB steps. The Stereo Mix signal feeds both the Line Out and Headphone Out analog outputs and is also selectable at the Record Select Mux. During Initialization or Cold Reset, (reset pin held active low), PC_BEEP is switched directly to both channels of the Line Out stereo output, bypassing all volume controls. This allows signals such as PC power-on self-test tones to be heard through the PC's audio system before the codec registers are configured.
PHONE	13	I	Mono Input This line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for conversion by either or both channels of the stereo ADC. It can also be mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can be muted or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. The Stereo Mix signal feeds both the Line Out and Headphone Out analog stereo outputs and is also selectable at the Record Select Mux.
AUX_L	14	I	Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_L level can be muted (along with AUX_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
AUX_R	15	I	Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Aux Volume register, 16h. The AUX_R level can be muted (along with AUX_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
VIDEO_L	16	I	Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level can be muted (along with VIDEO_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
VIDEO_R	17	I	Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_R level can be muted (along with VIDEO_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
CD_L	18	I	Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Input Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_L level can be muted (along with CD_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is mixed into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
CD_GND	19	I	AC Ground Reference This input is the reference for the signals on both CD_L and CD_R. CD_GND is NOT a DC ground and must be AC-coupled to the stereo source ground common to both CD_L and CD_R. The three inputs CD_GND, CD_L and CD_R act together as a quasi-differential stereo input with CD_GND providing AC common-mode feedback to reject ground noise. This can improve the input SNR for a stereo source with a good common ground but precision resistors may be needed in any external attenuators to achieve the necessary balance between the two channels.
CD_R	20	I	Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the CD Volume register, 12h. The CD_R level can be muted (along with CD_L) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
MIC1	21	I	Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the right or left channels of the Record Select Mux for conversion on either or both channels of the stereo ADC. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing adjustments through Mic Volume register, 0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to the stereo outputs Line Out and Headphone Out. Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h.
MIC2	22	I	Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The boost amplifier gain (0 dB or 20 dB) is set by the 20 dB bit (D6) in the Mic Volume register, 0Eh. Nominal input levels at the two gain settings are 1 Vrms and 0.1 Vrms respectively. The amplifier output is selectable (Record Select register, 1Ah) by either the right or left channels of the Record Select Mux for conversion on either or both channels of the stereo ADC. The amplifier output can also be accessed at the stereo mixer MIX1 (muting and mixing adjustments through Mic Volume register, 0Eh) where it is mixed equally into both left and right channels of Stereo Mix 3D for access to the stereo outputs Line Out and Headphone Out. Access to the Mono analog output is selected by a mux controlled by the MIX bit (D9) in General Purpose register, 20h.
LINE_IN_L	23	I	Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_L level can be muted (along with LINE_IN_R) or adjusted from 12 dB to –34.5 dB in 1.5-dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
LINE_IN_R	24	I	Right Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Input Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the Stereo Mix 3D signal at MIX1 under the control of the Line In Volume register, 10h. The LINE_IN_R level can be muted (along with LINE_IN_L) or adjusted from 12 dB to –34.5 dB in 1.5 dB steps. Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and Headphone Out.
LINE_OUT_L	35	O	Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2 through the Master Volume register, 02h. The LINE_OUT_L amplitude can be muted (along with LINE_OUT_R) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps.
LINE_OUT_R	36	O	Right Stereo Channel Output This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2 through the Master Volume register, 02h. The LINE_OUT_R amplitude can be muted (along with LINE_OUT_L) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps.
MONO_OUT	37	O	Mono Output This mono line level output (1 Vrms nominal) is fed from either a microphone input (MIC1 or MIC2, after boost amplifier) or from the mono sum of the left and right Stereo Mix 3D channels from MIX1. The optional TI 3D Sound enhancement can be disabled (default) by the 3D bit (bit D13) in the General Purpose register, 20h. Choice of input is by the MIX bit (D9) in the same register. MIX=0 selects a microphone input. Output level can be muted or adjusted from 0 dB to –46.5 dB in 1.5-dB steps through the Mono Volume register, 06h.
HP_OUT_L	39	O	Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal from MIX2 through the Headphone Volume register, 04h. The HP_OUT_L amplitude can be muted (along with HP_OUT_R) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps
HP_OUT_C	40	I	AC Ground Reference In normal use, this input is the AC ground reference for HP_OUT_L and HP_OUT_R. It must be capacitively coupled to analog ground with short traces to maximize performance. It is not a DC ground. For non-stereo applications it may also be used to provide common-mode feedback with HP_OUT configured as one differential output rather than as outputs for two single-ended stereo channels.
HP_OUT_R	41	O	Right Stereo Channel Output This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal from MIX2 through the Headphone Volume register, 04h. The HP_OUT_R amplitude can be muted (along with HP_OUT_L) or adjusted from 0 dB to –46.5 dB in 1.5-dB steps
DIGITAL I/O AND CLOCKING
XTL_IN	2	I	24.576 MHz crystal or external oscillator input To complete the oscillator circuit use a fundamental mode crystal operating in parallel resonance and connect a 1MΩ resistor across pins 2 and 3. Choose the load capacitors (Figure 25, C1, C2) to suit the load capacitance required by the crystal (that is, C1 = C2 = 33 pF for a 20 pF crystal. Assumes that each Input + trace capacitance is 7 pF). This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at standard logic levels (V_IH, V_IL). This pin is only used when the codec is in Primary mode. It may be left open (NC) for any Secondary mode.
XTL_OUT	3	O	24.576 MHz crystal output Used with XTAL_IN to configure a crystal oscillator. When the codec is used with an external oscillator this pin should be left open (NC). When the codec is configured in a Secondary mode this pin is not used and may be left open (NC).
SDATA_OUT	5	I	Input to codec This is the input for AC Link Output Frames from an AC '97 Digital Audio Controller to the LM4550B codec. These frames can contain both control data and DAC PCM audio data. This input is sampled by the LM4550B on the falling edge of BIT_CLK.
BIT_CLK	6	I/O	AC Link clock An OUTPUT when in Primary Codec mode. This pin provides a 12.288-MHz clock for the AC Link. The clock is derived (internally divided by two) from the 24.576-MHz signal at the crystal input (XTL_IN). This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and would normally use the AC Link clock generated by a Primary Codec.
SDATA_IN	8	O	Output from codec This is the output for AC Link Input Frames from the LM4550B codec to an AC '97 Digital Audio Controller. These frames can contain both codec status data and PCM audio data from the ADCs. The LM4550B clocks data from this output on the rising edge of BIT_CLK.
SYNC	10	I	AC Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is sampled on the falling edge of BIT_CLK and the codec takes the first positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored. SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is used to clear a power-down state on the codec AC Link interface.
RESET#	11	I	Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# MUST be used to initialize the LM4550B after Power On when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the LINE_OUT stereo output.
ID0#	45	I	Codec Identity ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will be set to 1. Similarly, connection to DV_DD will set the ID0 bit to 0. If left open (NC), ID0# is pulled high by an internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See the register description and the CIN pin description for details.
ID1#	46	I	Codec Identity ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit (D15, reg 28h) will be set to 1. Similarly, connection to DV_DD will set the ID1 bit to 0. If left open (NC), ID1# is pulled high by an internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See the register description and the CIN pin description for details.
EAPD	47	O	External Amplifier Power-Down control signal This output is set by the EAPD bit (bit D15) in the Power-down Control/Status register, 26h. As with the other logic outputs, the output voltage is set by DV_DD. This pin is intended to be connected to the shutdown pin on an external power amplifier. For normal operation the default value of EAPD = 0 will enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset.
CIN	48	I	Chain In The codec can be instructed to disconnect its own SDATA_IN signal and instead pass the signal on CIN through to the SDATA_IN output pin. This is achieved by changing the value of the two LSBs of the Chain-In Control register (74h) so that they differ from the Codec Identity bits ID1, ID0. Those two LSBs default to the value of the Codec Identity bits following Cold Reset thereby disabling the Chain In feature. Chain In can also be disabled by reading the Codec Identity from the Extended Audio ID register (28h) and writing the value back into register 74h LSBs. The Codec Identity bits are determined by the input pins ID1#, ID0#. CIN can be left open (NC) provided that the chain feature is disabled. When the chain feature is used, CIN should always be driven. Either connect the SDATA_IN pin from another codec or else ground CIN to prevent the possibility of floating the SDATA_IN signal at the controller.
POWER SUPPLIES AND REFERENCES
AV_DD1	25	I	Analog supply
AV_SS1	26	I	Analog ground
AV_DD2	38	I	Analog supply 2
AV_SS2	42	I	Analog ground 2
DV_DD1	1	I	Digital supply
DV_DD2	9	I	Digital supply
DV_SS1	4	I	Digital ground
DV_SS2	7	I	Digital ground
V_REF	27	O	Nominal 2.2-V internal reference Not intended to sink or source current. Use short traces to bypass (3.3 µF, 0.1 µF) this pin to maximize codec performance. See text.
V_{REF_OUT}	28	O	Nominal 2.2-V reference output Can source up to 5 mA of current and can be used to bias a microphone.
3D SOUND AND NO-CONNECTS (NC)
3DP	33	O	These pins are used to complete the TI 3D Sound stereo enhancement circuit. Connect a 0.022-µF capacitor between pins 3DP and 3DN. TI 3D Sound can be turned on and off though the 3D bit (bit D13) in the General Purpose register, 20h. TI 3D Sound uses a fixed-depth type stereo enhancement circuit hence the 3D Control register, 22h is read-only and is not programmable. If TI 3D Sound is not needed, these pins should be left open (NC).
3DN	34	O
NC	29	NC	These pins are not used and should be left open (NC). For second source applications these pins may be connected to a noise-free supply or ground (that is, AV_DD or AV_SS), either directly or through a capacitor.
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