ZHCSDU6B July   2012  – July 2015 LM4549B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC Inputs and Outputs
      2. 8.3.2  Analog Mixing: MIX1
      3. 8.3.3  DAC Mixing and 3D Processing
      4. 8.3.4  Analog Mixing: MIX2
      5. 8.3.5  Stereo Mix
      6. 8.3.6  Stereo Outputs
      7. 8.3.7  Mono Output
      8. 8.3.8  Analog Loopthrough and Digital Loopback
      9. 8.3.9  Resets
      10. 8.3.10 Backwards Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Modes
      2. 8.4.2 Test Modes
    5. 8.5 Programming
      1. 8.5.1 AC Link Serial Interface Protocol
        1. 8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4549B Input
          1. 8.5.1.1.1 SDATA_OUT: Slot 0 - Tag Phase
          2. 8.5.1.1.2 SDATA_OUT: Slot 1 - Read/Write, Control Address
          3. 8.5.1.1.3 SDATA_OUT: Slot 2 - Control Data
          4. 8.5.1.1.4 SDATA_OUT: Slots 3 & 4 - PCM Playback Left/Right Channels
          5. 8.5.1.1.5 SDATA_OUT: Slots 5 to 12 - Reserved
        2. 8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4549B Output
          1. 8.5.1.2.1 SDATA_IN: Slot 0 - Codec/Slot Status Bits
          2. 8.5.1.2.2 SDATA_IN: Slot 1 - Status Address / Slot Request Bits
          3. 8.5.1.2.3 SDATA_IN: Slot 2 - Status Data
          4. 8.5.1.2.4 SDATA_IN: Slot 3 - PCM Record Left Channel
          5. 8.5.1.2.5 SDATA_IN: Slot 4 - PCM Record Right Channel
          6. 8.5.1.2.6 SDATA_IN: Slots 5 to 12 - Reserved
      2. 8.5.2 Multiple Codecs
        1. 8.5.2.1 Extended AC Link
        2. 8.5.2.2 Secondary Codec Register Access
          1. 8.5.2.2.1 Slot 0: TAG bits in Output Frames (Controller to Codec)
          2. 8.5.2.2.2 Extended Audio ID register (28h): Support for Multiple Codecs
    6. 8.6 Register Maps
      1. 8.6.1  Reset Register (00h)
      2. 8.6.2  Master Volume Register (02h)
      3. 8.6.3  Line Level Volume Register (04h)
      4. 8.6.4  Mono Volume Register (06h)
      5. 8.6.5  PC Beep Volume Register (0Ah)
      6. 8.6.6  Mixer Input Volume Registers (Index 0Ch - 18h)
      7. 8.6.7  Record Select Register (1Ah)
      8. 8.6.8  Record Gain Register (1Ch)
      9. 8.6.9  General Purpose Register (20h)
      10. 8.6.10 3D Control Register (22h)
      11. 8.6.11 Power-Down Control / Status Register (26h)
      12. 8.6.12 Extended Audio ID Register (28h)
      13. 8.6.13 Extended Audio Status/Control register (2Ah)
      14. 8.6.14 Sample Rate Control Registers (2Ch, 32h)
      15. 8.6.15 Vendor ID Registers (7Ch, 7Eh)
      16. 8.6.16 Reserved Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 System Example
      1. 9.3.1 Improving System Performance
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

13 机械、封装和可订购信息

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