SNVS656D September   2010  – October 2016 LM3492 , LM3492-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Switching Frequency
      2. 8.3.2 LDO Regulator
      3. 8.3.3 Enable and Disable
      4. 8.3.4 Current Limit
      5. 8.3.5 Thermal Protection
      6. 8.3.6 Dynamic Headroom Control, Over-Ride, and Soft-Start
      7. 8.3.7 Current Regulator
      8. 8.3.8 Output Voltage Feedback
      9. 8.3.9 Bidirectional Communication Pin
        1. 8.3.9.1 Power-Good Indication
        2. 8.3.9.2 Overtemperature Indication
        3. 8.3.9.3 Output Current Undervoltage Indication
        4. 8.3.9.4 Switching Frequency Tuning
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Output Current Overvoltage Indication
      2. 8.5.2 COMM Pin Bit Pattern
      3. 8.5.3 Channel 1 Disable
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 RFB1, RFB2, and CFB
        2. 9.2.2.2 L1
        3. 9.2.2.3 D1
        4. 9.2.2.4 CIN and COUT
        5. 9.2.2.5 CVCC
        6. 9.2.2.6 CCDHC
        7. 9.2.2.7 RRT and RIREF
        8. 9.2.2.8 RCOMM
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

PWP PowerPAD™ Package
20-Pin HTSSOP
Top View
LM3492 LM3492-Q1 30116102.png

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NO. NAME
1 EN I Enable Internally pullup. Connect to a voltage higher than 1.63 V to provide precision enable for the device.
2 VIN I Input Supply Voltage Supply pin to the device. Input range is 4.5 V to 65 V.
3 SW I Switch Node Internally connected to the drain of the integrated MOSFET.
4
5 VOUT I Output Voltage Sense Sense the output voltage for nearly constant switching frequency control.
6 RT I Frequency Control An external resistor from the VOUT pin to this pin sets the switching frequency.
7 FB I Output Voltage Feedback The output voltage is connected to this pin through a feedback resistor divider for output voltage regulation. The voltage of this pin is from 1.05 V to 2.5 V.
8 GND G Analog Ground Signal ground
9 IOUT2 I Current Regulator Input of Channel 2 Input of the current regulator of channel 2. The regulated current is programmable (refer to the IREF pin).
10 IOUT1 I Current Regulator Input of Channel 1 Input of the current regulator of channel 1. The regulated current is programmable (refer to the IREF pin).
11 CDHC I Dynamic Headroom
Control		 An external capacitor connected to this pin sets the DHC sensitivity. At start-up, a 120-µA internal current source charges an external capacitor to provide a soft-start function.
12 IREF I Current Setting of the
Current Regulator		 An external resistor connected from this pin to ground programs the regulated current of the current regulator of channels 1 and 2.
13 COMM I/O Bidirectional Logic Communication This pin is open drain for various indications (power-good, overtemperature, IOUT overvoltage and undervoltage) and command sending (switching frequency tuning and channel 1 disabling).
14 LGND G Ground of the Current Regulator Current regulator ground. Must be connected to the GND pin for normal operation. The LGND and GND pins are not internally connected.
15 DIM1/CLK I/O Dimming Control of
Channel 1		 Control the ON/OFF of the current regulator of channel 1. This pin is internally pulled low by a 5-µA current. This pin also serves as a clock signal for latching input/output data of the COMM pin.
16 DIM2 I Dimming Control of
Channel 2		 Control the ON/OFF of the current regulator of channel 2. This pin is internally pulled low by a 5-µA current.
17 PGND G Power Ground Integrated MOSFET ground. Must be connected to the GND pin for normal operation. The PGND and GND pins are not internally connected.
18
19 VCC O LDO Regulator Output Nominally regulated to 5.5 V. Connect a capacitor of larger than 0.47 µF between the VCC and GND pins.
20 ILIM I Peak Current Limit Adjust Connect an external resistor from the ILIM pin to the VCC pin reduces peak current limit. Connect the ILIM pin to the ground to obtain the maximum current limit.
DAP DAP — Exposed Pad Thermal connection pad. Connect to a ground plane.