SNVS009H November   1999  – March 2016 LM2665

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuit
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Circuit Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Voltage Doubler
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Requirements
          1. 9.2.1.2.1 Positive Voltage Doubler
          2. 9.2.1.2.2 Capacitor Selection
          3. 9.2.1.2.3 Paralleling Devices
          4. 9.2.1.2.4 Cascading Devices
          5. 9.2.1.2.5 Regulating VOUT
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Splitting V+ In Half
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The LM2665 CMOS charge-pump voltage converter operates as a voltage doubler for an input voltage in the range of 2.5 V to 5.5 V. Two low-cost capacitors and a diode (needed during start-up) are used in this circuit to provide up to 40 mA of output current. The LM2665 can also work as a voltage divider to split a voltage in the range of 1.8 V to 11 V in half.

8.2 Functional Block Diagram

LM2665 blockdiag.gif

8.3 Feature Description

8.3.1 Circuit Description

The LM2665 contains four large CMOS switches which are switched in a sequence to double the input supply voltage. Energy transfer and storage are provided by external capacitors. Figure 10 illustrates the voltage conversion scheme. When S2 and S4 are closed, C1 charges to the supply voltage V+. During this time interval, switches S1 and S3 are open. In the next time interval, S2 and S4 are open; at the same time, S1 and S3 are closed, the sum of the input voltage V+ and the voltage across C1 gives the 2-V+ output voltage when there is no load. The output voltage drop when a load is added is determined by the parasitic resistance (RDS(on) of the MOSFET switches and the ESR of the capacitors) and the charge transfer loss between capacitors. Details are discussed in Application and Implementation.

LM2665 10004914.png Figure 10. Voltage Doubling Principle

8.4 Device Functional Modes

8.4.1 Shutdown Mode

A shutdown (SD) pin is available to disable the device and reduce the quiescent current to 1 µA. In normal operating mode, the SD pin is connected to ground. The device can be brought into the shutdown mode by applying to the SD pin a voltage greater than 40% of the V+ pin voltage.