10.1 Pcb Layout Considerations

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched at high slew rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 37). To minimize both loop areas, the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitor should be close. Ideally, a ground plane should be placed on the top layer that connects the PGND pins, the exposed pad (EP) of the device, and the ground connections of the input and output capacitors in a small area near pin 10 and 11 of the device. The inductor should be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. The six SW pins should be routed on a single top plane to the pad of the inductor. The inductor should be placed as close as possible to the switch pins of the device with a wide trace to minimize conductive losses. The inductor can be placed on the bottom side of the PCB relative to the LM21212-1, but care must be taken to not allow any coupling of the magnetic field of the inductor into the sensitive feedback or compensation traces.
3. Have a solid ground plane between PGND, the EP and the input and output cap. ground connections. The ground connections for the AGND, compensation, feedback, and soft-start components should be physically isolated (located near pin 1 and 20) from the power ground plane but a separate ground connection is not necessary. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior.
4. Carefully route the connection from the VOUT signal to the compensation network. This node is high impedance and can be susceptible to noise coupling. The trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy.
6. Provide adequate device heatsinking. For most 12A designs a four layer board is recommended. Use as many vias as is possible to connect the EP to the power plane heatsink. The vias located underneith the EP will wick solder into them if they are not filled. Complete solder coverage of the EP to the board is required to achieve the θ_JA values described in the previous section. Either an adequate amount of solder must be applied to the EP pad to fill the vias, or the vias must be filled during manufacturing. See the Thermal Considerations section to ensure enough copper heatsinking area is used to keep the junction temperature below 125°C.

Figure 37. Schematic Of Lm21212-1 Highlighting Layout Sensitive Nodes

Figure 38. Typical Application Schematic 1

Figure 39. Typical Application Schematic 2