ZHCSCX2E 数据表 | 德州仪器 TI.com.cn

ZHCSCX2E January 2014 – October 2017 LM15851

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NKE|68
- MPQS033A

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6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
DEVICE (SAMPLING) CLOCK
ƒ_(DEVCLK)	Input DEVCLK frequency	Sampling rate is equal to clock input	1		4	GHz
t_d(A)	Sampling (aperture) delay	Input CLK transition to sampling instant		0.64		ns
t_(AJ)	Aperture jitter			0.1		ps RMS
t_{(LAT_DDC)}	ADC core and DDC latency⁽²⁾	Decimation = 4, DDR = 1, P54 = 0		292		t_(DEVCLK)
		Decimation = 4, DDR = 1, P54 = 1		284
		Decimation = 8, DDR = 0, P54 = 0		384
		Decimation = 8, DDR = 0, P54 = 1		368
		Decimation = 8, DDR = 1, P54 = 0		392
		Decimation = 8, DDR = 1, P54 = 1		368
		Decimation = 10, DDR = 0, P54 = 0		386
		Decimation = 10, DDR = 1, P54 = 0		386
		Decimation = 16, DDR = 0, P54 = 0		608
		Decimation = 16, DDR = 0, P54 = 1		560
		Decimation = 16, DDR = 1, P54 = 0		608
		Decimation = 16, DDR = 1, P54 = 1		560
		Decimation = 20, DDR = 0, P54 = 0		568
		Decimation = 20, DDR = 1, P54 = 0		568
		Decimation = 32, DDR = 0, P54 = 0		1044
		Decimation = 32, DDR = 0, P54 = 1		948
		Decimation = 32, DDR = 1, P54 = 0		1044
JESD204B INTERFACE LINK TIMING CHARACTERISTICS (REFER TO Figure 1)
t_d(LMFC)	SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary⁽²⁾	All decimation modes		40		t_(DEVCLK)
t_d(TX)	LMFC to frame boundary delay - decimation modes Functional delay from LMFC frame boundary to beginning of next multi-frame in transmitted data⁽³⁾	Decimation = 4, DDR = 1, P54 = 0		52.7		t_(DEVCLK)
		Decimation = 4, DDR = 1, P54 = 1		43.9
		Decimation = 8, DDR = 0, P54 = 0		60.7
		Decimation = 8, DDR = 0, P54 = 1		51.5
		Decimation = 8, DDR = 1, P54 = 0		52.7
		Decimation = 8, DDR = 1, P54 = 1		43.9
		Decimation = 10, DDR = 0, P54 = 0		60.7
		Decimation = 10, DDR = 1, P54 = 0		52.7
		Decimation = 16, DDR = 0, P54 = 0		60.7
		Decimation = 16, DDR = 0, P54 = 1		51.5
		Decimation = 16, DDR = 1, P54 = 0		52.7
		Decimation = 16, DDR = 1, P54 = 1		43.9
		Decimation = 20, DDR = 0, P54 = 0		60.7
		Decimation = 20, DDR = 1, P54 = 0		52.7
		Decimation = 32, DDR = 0, P54 = 0		60.7
		Decimation = 32, DDR = 0, P54 = 1		51.5
		Decimation = 32, DDR = 1, P54 = 0		52.7
t_su(SYNC~-F)	SYNC~ to LMFC setup time⁽¹⁾ Required SYNC~ setup time relative to the internal LMFC boundary.			40		t_(DEVCLK)
t_h(SYNC~-F)	SYNC~ to LMFC hold time⁽¹⁾ Required SYNC~ hold time relative to the internal LMFC boundary.			–8		t_(DEVCLK)
t_(SYNC~)	SYNC~ assertion time Required SYNC~ assertion time before deassertion to initiate a link resynchronization.			4		Frame clock cycles
t_d(LMFC)	Delay from SYSREF sampled high by DEVCLK to internal LMFC boundary			40		t_(DEVCLK)
t_(ILA)	Duration of initial lane alignment sequence			4		Multi-frame clock cycles
SYSREF
t_su(SYS)	Setup time SYSREF relative to DEVCLK rising edge⁽⁶⁾			40		ps
t_h(SYS)	Hold time SYSREF relative to DEVCLK rising edge⁽⁶⁾			40		ps
t_{(PH_SYS)}	SYSREF assertion duration after rising edge event.		8			t_(DEVCLK)
t_{(PL_SYS)}	SYSREF deassertion duration after falling edge event.		8			t_(DEVCLK)
t_(SYS)	Period SYSREF±	DDR = 0, P54 = 0		K × F × 10		t_(DEVCLK)
		DDR = 0, P54 = 1		K × F × 8
		DDR = 1, P54 = 0		K × F × 5
		DDR = 1, P54 = 1		K × F × 4
SERIAL INTERFACE (REFER TO Figure 2)
ƒ_(SCK)	Serial clock frequency⁽²⁾				20	MHz
t_(PH)	Serial clock high time		20			ns
t_(PL)	Serial clock low time		20			ns
t_su	Serial-data to serial-clock rising setup time⁽²⁾		10			ns
t_h	Serial-data to serial clock rising hold time⁽²⁾		10			ns
t_(CSS)	SCS-to-serial clock rising setup time		10			ns
t_(CSH)	SCS-to-serial clock falling hold time		10			ns
t_(IAG)	Inter-access gap		10			ns

(1) This parameter must be met to achieve deterministic alignment of the data frame and NCO phase to other similar devices. If this parameter is not met the device will still function correctly but will not be aligned to other devices.

(2) Unless otherwise specified, delays quoted are exact un-rounded functional delays (assuming zero propagation delay).

(3) The values given are functional delays only. Additional propagation delay of 0 to 3 clock cycles will be present.