ZHCSKG9 November 2019 LDC1001-Q1
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | SCLK | DI | SPI clock input. The SCLK pin is used to clock-out and clock-in the data from or into the chip |
| 2 | CSB | DI | SPI CSB. Multiple devices can be connected on the same SPI bus and the CSB pin can be used to select which device is communicated with. |
| 3 | SDI | DI | SPI Slave Data In (Master Out Slave In). This pin should be connected to the Master Out Slave In of the master device. |
| 4 | VIO | P | Digital IO Supply |
| 5 | SDO | DO | SPI Slave Data Out (Master In Slave Out). This pin is high-Z when the CSB pin is high. |
| 6 | DGND | P | Digital ground |
| 7 | CFB | A | LDC filter capacitor |
| 8 | CFA | A | LDC filter capacitor |
| 9 | INA | A | External LC Tank. Connect this pin to an external LC tank. |
| 10 | INB | A | External LC Tank. Connect this pin to an external LC tank. |
| 11 | GND | P | Analog ground |
| 12 | VDD | P | Analog supply |
| 13 | CLDO | A | LDO bypass capacitor. Connect a 56-nF capacitor from this pin to GND. |
| 14 | TBCLK | DI | External time-base clock |
| 15 | NC | NC | This pin should be floating. |
| 16 | INTB | DO | Configurable interrupt. This pin can be configured to function in three different ways (threshold detect, wake-up, or DRDYB) by programing the INT pin mode register. |