11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in².
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
• While routing differential traces on a board, TI recommends that the distance between two differential pairs be much higher (at least 2x) than the distance between the traces in a differential pair. This distance minimizes crosstalk between the two differential pairs.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

The ISO7821LLS device requires no special layout considerations to mitigate electromagnetic emissions.

For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).

11.2 Layout Example

Figure 31. Layout Example