ZHCSSZ3H May   2008  – August 2023 ISO15 , ISO35

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: Driver
    10. 6.10 Electrical Characteristics: Receiver
    11. 6.11 Supply Current
    12. 6.12 Switching Characteristics: Driver
    13. 6.13 Switching Characteristics: Receiver
    14. 6.14 Insulation Characteristics Curves
    15. 6.15 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Device Functional Modes
      1. 8.3.1 Device I/O Schematics
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  11.   Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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Pin Configuration and Functions

GUID-46968D4A-48E6-4D8A-A0C9-16828BD3CC0D-low.gifFigure 5-1 ISO35x DW Package
16-Pin SOIC
Top View
GUID-88070CEF-8CBF-4A90-B519-96318516B8F8-low.gifFigure 5-2 ISO15x DW Package
16-Pin SOIC
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME ISO15x
NO.
ISO35x
NO.
A 12 14 I/O ISO15x: Noninverting bus input or output
I ISO35x: Noninverting bus input
B 13 13 I/O ISO15x: Inverting bus input or output
I ISO35x: Inverting bus input
D 6 6 I Driver input
DE 5 5 I Driver logic-high enable input
GND1 2,7,8 2,7,8 Logic side ground; internally connected
GND2 9,10,15 9,10,15 Bus side ground; internally connected
NC 11,14 Not connected internally; may be left floating
R 3 3 O Receiver output
RE 4 4 I Receiver logic-low enable
VCC1 1 1 Logic side power supply
VCC2 16 16 Bus side power supply
Y 11 O Noninverting bus output
Z 12 O Inverting bus output