ZHCSSZ5F march   2008  – august 2023 ISO1176

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: Driver
    10. 6.10 Electrical Characteristics: Receiver
    11. 6.11 Supply Current
    12. 6.12 Electrical Characteristics: ISODE-Pin
    13. 6.13 Switching Characteristics: Driver
    14. 6.14 Switching Characteristics: Receiver
    15. 6.15 Insulation Characteristics Curves
    16. 6.16 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Voltages
        2. 9.2.2.2 ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6.10 Electrical Characteristics: Receiver

All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage
IO = –8 mA, See Figure 22
 		 -80 –10 mV
VIT– Negative-going input threshold voltage
IO = 8 mA, See Figure 22
 		 –200 -120 mV
Vhys Input hysteresis (VIT+ – VIT–) 40 mV
VOH Output Voltage VCC1 at 3.3 V and VCC2 at 5V, VID = 200mV, IO = -8mA VCC1-0.4 3 V
VOH Output Voltage VCC1 at 3.3 V and VCC2 at 5V, VID = 200mV, IO = -20uA VCC1-0.1 3.3 V
VOL Output Voltage VCC1 at 3.3 V and VCC2 at 5V, VID = -200mV, IO = 8mA 0.2 0.4 V
VOL Output Voltage VCC1 at 3.3 V and VCC2 at 5V, VID = -200mV, IO = 20uA 0 0.1 V
VOH Output Voltage VCC1 at 5 V and VCC2 at 5V, VID = 200mV, IO = -8mA VCC1-0.8 4.6 V
VOH Output Voltage VCC1 at 5 V and VCC2 at 5V, VID = 200mV, IO = -20uA VCC1-0.1 5 V
VOL Output Voltage VCC1 at 5 V and VCC2 at 5V, VID = -200mV, IO = 8mA 0.2 0.4 V
VOL Output Voltage VCC1 at 5 V and VCC2 at 5V, VID = -200mV, IO = 20uA 0 0.1 V

IA or IB
 
Bus pin input current
 		 VI = -7 V or 12 V, other input = 0V: VCC = 4.75 V or 5.25 V -160 200 µA

IA(OFF) or IB(OFF)
 		 VI = -7 V or 12 V, other input = 0V: VCC2 = 0 V

II
 
Receiver enable input current
 
RE = 0 V or VCC1
 		 -50 50 µA
IOZ High impedance state output current
RE = VCC1
 		 –1 1 µA
RID
Differential input resistance


A, B

48 kohm
CID
Differential input capacitance


Test input signal is a 1.5MHz sine wave with 1VPP amplitude, CD is measured across A and B
 		 7 10 pF
CMR Common mode rejection See Figure 26 4 V