ZHCSSZ5F march   2008  – august 2023 ISO1176

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: Driver
    10. 6.10 Electrical Characteristics: Receiver
    11. 6.11 Supply Current
    12. 6.12 Electrical Characteristics: ISODE-Pin
    13. 6.13 Switching Characteristics: Driver
    14. 6.14 Switching Characteristics: Receiver
    15. 6.15 Insulation Characteristics Curves
    16. 6.16 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Voltages
        2. 9.2.2.2 ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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Overview

The ISO1176 is an isolated half-duplex differential line transceiver that meets the requirements of EN 50170 and TIA/EIA 485/422 applications. The device is rated to provide galvanic isolation of up to 2500 VRMS for 60 s per UL 1577. The device has active-high driver enable and active-low receiver enable functions to control the data flow. The device has maximum data transmission speed of 40 Mbps.

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = V(A) – V(B) is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT– , the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).