ZHCSAQ1D February 2013 – July 2022 INA231
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The Mask/Enable register selects the function that controls the ALERT pin, as well as how that pin functions. If multiple functions are enabled, the highest significant bit position alert function (D15:D11) takes priority and responds to the Alert Limit register.
| BIT # | D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BIT NAME | SOL | SUL | BOL | BUL | POL | CNVR | — | — | — | — | — | AFF | CVRF | OVF | APOL | LEN |
| POR VALUE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| SOL: | Shunt Voltage Overvoltage1 |
| Bit 15 | Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion exceeds the value in the Alert Limit register. |
| SUL: | Shunt Voltage Undervoltage |
| Bit 14 | Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion drops below the value in the Alert Limit register. |
| BOL: | Bus Voltage Overvoltage |
| Bit 13 | Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion exceeds the value in the Alert Limit register. |
| BUL: | Bus Voltage Undervoltage |
| Bit 12 | Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion drops below the value in the Alert Limit register. |
| POL: | Power Overlimit |
| Bit 11 | Setting this bit high configures the ALERT pin to be asserted when the power calculation exceeds the value in the Alert Limit register. |
| CNVR: | Conversion Ready |
| Bit 10 | Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag bit (CVRF, bit 3) is asserted, indicating that the device is ready for the next conversion. |
| AFF: | Alert Function Flag |
| Bit 4 | Although only one alert function at a time can be monitored at the ALERT pin, the Conversion Ready bit (CNVR, bit 10) can also be enabled to assert the ALERT pin. Reading the Alert Function Flag bit after an alert can help determine if the alert function was the source of the alert. When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared after the next conversion that does not result in an alert condition. |
| CVRF: | Conversion Ready Flag |
| Bit 3 | Although the INA231 can be read at any time, and the data from the last conversion are available, this bit is provided to help coordinate single-shot or triggered conversions. This bit is set after all conversions, averaging, and multiplications are complete. This bit clears under the following conditions in single-shot mode:
1) Writing to the Configuration register (except for power-down or disable selections) 2) Reading the Mask/Enable register |
| OVF: | Math Overflow Flag |
| Bit 2 | This bit is set to 1 if an arithmetic operation results in an overflow error; it indicates that current and power data may be invalid. |
| APOL: | Alert Polarity |
| Bit 1 | Configures the latching feature of the ALERT pin and the flag bits. 1 = Inverted (active-high open collector) 0 = Normal (active-low open collector) (default) |
| LEN: | Alert Latch Enable |
| Bit 0 | Configures the latching feature of the ALERT pin and flag bits. 1 = Latch enabled0 = Transparent (default) When the Alert Latch Enable bit is set to Transparent mode, the ALERT pin and flag bits reset to their idle states when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and flag bits remain active following a fault until the Mask/Enable register has been read. |