ZHCSAP4M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from L Revision (February 2017) to M Revision

  • 将修订版 L 中以前所做的所有 MLCK 内容更改恢复为修订版 KGo
  • Removed disable jitter cleaner noteGo

Changes from K Revision (January 2015) to L Revision

  • Changed top view pin out diagram Go
  • Changed CLK to RES2 Go
  • Added note to disable jitter cleaner Go
  • Changed MCLK to RES2 Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLK Go
  • Deleted I2S Jitter Cleaning section Go
  • Deleted MCLK section Go
  • Deleted MCLK columns in the Audio Interface Frequencies tableGo
  • Changed values in columns 2 to 5 of Configuration Select (MODE_SEL) tableGo
  • Changed values in columns 2 to 5 of IDx table Go
  • Changed Removed register reference to MCLKGo
  • Changed Typical Display System Diagram (removed MCLK) Go
  • Changed Power-Up Requirements and PDB pin description and added Power-Up Sequence graphic. Go

Changes from J Revision (April 2013) to K Revision

  • Added 引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from I Revision (August 2012) to J Revision

  • 将美国国家半导体产品说明书的布局更改为 TI 格式Go

Changes from H Revision (March 2012) to I Revision

  • ：配置选择 (MODE_SEL) #6 I2S 通道 B（18 位模式）从 L 到 H，将“直流和交流串行控制总线特征”表中的拼写错误从 VDDIO 纠正为 VDD33，添加了“推荐 FRC 设置表”，在“功能说明”部分下添加了“当向后兼容模式 = ON 时， LFMODE 设置 = 0”。重新设置了表格 9 的格式，并添加了澄清说明。在“功能说明、降低 EMI 特性、扩频时钟发生器 (SSCG)”部分下添加了“有关串行控制总线寄存器，地址 0x02[3:0]（向后兼容和 LFMODE 寄存器）的澄清说明”，添加了 “注意：如果进入 SER 的 PCLK 源 已经有一个 SSC 时钟，请勿启用 SSCG 功能。”Go

Changes from G Revision (February 2012) to H Revision

  • 删除了“直流电气特性”下的 PDB VDDIO = 1.71 至 1.89V，在“电源电流”下添加了 IDDZ、DDIOZ、IDDIOZ 最大值 = 10mA”，在“CML 显示器驱动程序输出交流规范”下，添加了 EW 最小值 = 0.3 UI 和 EH 最小值 = 200mV，在“功能说明”部分添加了“中断引脚 — 功能 说明 及使用 (INTB)” ， 更新了“功能说明” 部分下的 “断电 (PDB) 说明” 将 VDDIO 更新为 VDDIO = 3 至 3.6V 或 VDD33”，更新了图 24 Go