ZHCSAP4M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

Design the circuit board layout and stack-up for the FPD-Link III devices to provide low-noise power feed to the device. Good layout practice also separates high-frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50 µF to 100 µF range and will smooth low-frequency switching noise. TI recommends connecting the power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path.

TI recommends a small body size X7R chip capacitor, such as 0603 or 0402, for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Table 13:

Table 13. No Pullback WQFN Stencil Aperture Summary

DEVICE PIN COUNT MKT Dwg PCB I/O Pad Size (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O
APERTURE (mm)
STENCIL DAP
Aperture (mm)
NUMBER of DAP
APERTURE OPENINGS
DS90UH926Q-Q1 60 NKB0060B 0.25 × 0.6 0.5 6.3 × 6.3 0.25 × 0.8 6.3 × 6.3 1

Figure 29 shows the PCB layout example derived from the layout design of the DS90UH926QSEVB Evaluation Board. The graphic and layout description are used to determine both proper routing and proper solder techniques when designing the Serializer board.

CML Interconnect Guidelines

See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission Line RAPIDESIGNER® Operation and Applications Guide (SNLA035) for full details.

  • Use 100-Ω coupled differential pairs
  • Use the S/2S/3S rule in spacings
    • S = space between the pair
    • 2S = space between pairs
    • 3S = space to LVCMOS signal
  • Minimize the number of Vias
  • Use differential connectors when operating above 500 Mbps line speed
  • Maintain balance of the traces
  • Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI web site at: www.ti.com/lvds.

Layout Examples

DS90UH926Q-Q1 layout_snls422.gif Figure 29. DS90UH926Q-Q1 Deserializer Example Layout
DS90UH926Q-Q1 mpqs030.png Figure 30. 60-Pin WQFN Stencil Example of Via and Opening Placement