ZHCSFV6E august   2016  – november 2020 DS90UB933-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB933/934
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB933/934 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 62
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from Revision D (January 2020) to Revision E (November 2020)

  • Added register 0x27[3] to register mapGo
  • Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH Go
  • Changed Power-Up Sequencing alternative programming steps (t3*) to add NCLK resetGo
  • Clarified Power-Up Sequencing alternative programming steps (t3*) to remove delay between I2C commands Go

Changes from Revision C (November 2019) to Revision D (January 2020)

  • Clarified GPO2 description by removing statement about leaving pin open if unused Go
  • Added maximum power up timing constraint between VDD_n and PDB Go
  • Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint can not be met Go

Changes from Revision B (September 2018) to Revision C (November 2019)

  • Added register 0x27[5] to register map Go

Changes from Revision A (December 2016) to Revision B (September 2018)

  • Added recommendation to ensure GPO2 is low when PDB goes highGo
  • Added external clock input frequency range Go
  • Added strap pin input current specification for MODE and IDX pins Go
  • Updated TJIT1 PCLK input jitter in the external oscillator modeGo
  • Added that 0.45UI TJIT2 maximum is when used with DS90UB934-Q1 and added new foot note Go
  • Added clarification on MODE pin description in PCLK from imager mode Go
  • Updated the MODE setting values to ratio from voltageGo
  • Updated IDX setting values to ratio from voltageGo
  • Added register "TYPE" column per legend Go
  • Added type and default value to the reserved register bits that were missing this informationGo
  • Added that register 0x00[7:1] does not auto update IDX strapped address Go
  • Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b)Go
  • Added reference to Power over Coax Application reportGo
  • Clarified description on PDB pin usage during power up Go
  • Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high Go
  • Added GPO2 to suggested power-up sequencing diagram Go
  • timing constraint for PDB to GPO2 delay Go
  • Revised coax connection diagram to include pulldown resistor for GPO2 Go
  • Revised STP connection diagram to include pulldown resistor for GPO2 Go

Changes from Revision * (August 2016) to Revision A (December 2016)

  • 将“产品预发布”更改为“量产数据发布”。Go