ZHCSDZ6D July   2012  – July 2015 DS90UB913Q-Q1 , DS90UB914Q-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 器件比较表
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements: Recommended for Serializer PCLK
    7. 8.7  AC Timing Specifications (SCL, SDA) - I2C Compliant
    8. 8.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant
    9. 8.9  Switching Characteristics: Serializer
    10. 8.10 Switching Characteristics: Deserializer
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 AC Timing Diagrams and Test Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Frame Format
      2. 10.3.2  Line Rate Calculations for the DS90UB91xQ
      3. 10.3.3  Deserializer Multiplexer Input
      4. 10.3.4  Error Detection
      5. 10.3.5  Description of Bidirectional Control Bus and I2C Modes
      6. 10.3.6  Slave Clock Stretching
      7. 10.3.7  I2C Pass-Through
      8. 10.3.8  ID[x] Address Decoder on the Serializer
      9. 10.3.9  ID[x] Address Decoder on the Deserializer
      10. 10.3.10 Programmable Controller
      11. 10.3.11 Synchronizing Multiple Cameras
      12. 10.3.12 General-Purpose I/O (GPIO) Descriptions
      13. 10.3.13 LVCMOS VDDIO Option
      14. 10.3.14 Deserializer - Adaptive Input Equalization (AEQ)
      15. 10.3.15 EMI Reduction
        1. 10.3.15.1 Deserializer Staggered Output
        2. 10.3.15.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
    4. 10.4 Device Functional Modes
      1. 10.4.1  DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock
      2. 10.4.2  DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock
      3. 10.4.3  MODE Pin on Serializer
      4. 10.4.4  MODE Pin on Deserializer
      5. 10.4.5  Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      6. 10.4.6  Multiple Device Addressing
      7. 10.4.7  Powerdown
      8. 10.4.8  Pixel Clock Edge Select (TRFB / RRFB)
      9. 10.4.9  Power-Up Requirements and PDB Pin
      10. 10.4.10 Built-In Self Test
      11. 10.4.11 BIST Configuration and Status
        1. 10.4.11.1 Sample BIST Sequence
    5. 10.5 Register Maps
  11. 11Application and Implementation
    1. 11.1 Applications Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Transmission Media
        2. 11.2.1.2 Adaptive Equalizer - Loss Compensation
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 相关链接
    3. 14.3 社区资源
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

RTV Package
32-Pin WQFN
Top View
DS90UB913Q-Q1 DS90UB914Q-Q1 30144619.gif

DS90UB913Q-Q1 Serializer Pin Functions

PIN I/O DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
DIN[0:11] 19, 20, 21,
22, 23, 24,
26, 27, 29,
30, 31, 32		 Inputs, LVCMOS
with pulldown		 Parallel data inputs
HSYNC 1 Inputs, LVCMOS
with pulldown		 Horizontal SYNC input
PCLK 3 Input, LVCMOS
with pulldown		 Pixel clock input pin
Strobe edge set by TRFB control register.
VSYNC 2 Inputs, LVCMOS
with pulldown		 Vertical SYNC input
GENERAL-PURPOSE OUTPUT (GPO)
GPO[1:0] 16, 15 Output, LVCMOS General-purpose output pins can be configured as outputs; used to control and respond to various commands. GPO[0:1] can be configured to be the outputs for input signals coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of the local register on the serializer.
GPO[2]/
CLKOUT		 17 Output, LVCMOS GPO2 pin can be configured to be the output for input signal coming from the GPIO2 pin on the deserializer or can be configured to be the output of the local register on the serializer. It can also be configured to be the output clock pin when the DS90UB913Q-Q1 device is used in the External Oscillator mode. See Applications Information for a detailed description of the DS90UB91xQ-Q1 chipsets working with the external oscillator.
GPO[3]/
CLKIN		 18 Input/Output, LVCMOS GPO3 can be configured to be the output for input signals coming from the GPIO3 pin on the deserializer or can be configured to be the output of the local register setting on the serializer. It can also be configured to be the input clock pin when the DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working with an external oscillator.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL 4 Input/Output,
Open-Drain		 Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO.
SDA 5 Input/Output,
Open-Drain		 Data line for the bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO.
MODE 8 Input, LVCMOS
with pulldown		 Device mode select
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the serializer can be used to select whether the system is running off the PCLK from the imager or an external oscillator. See details in Table 3.
ID[x] 6 Input, analog Device ID address select
The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 1.
CONTROL AND CONFIGURATION
PDB 9 Input, LVCMOS
with pulldown		 Power down Mode Input Pin
PDB = H, serializer is enabled and is ON.
PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values
RES 7 Input, LVCMOS
with pulldown		 Reserved
This pin MUST be tied LOW.
FPD-Link III INTERFACE
DOUT+ 13 Input/Output, CML Noninverting differential output, bidirectional control channel input. The interconnect must be AC-coupled with a 100-nF capacitor.
DOUT– 12 Input/Output, CML Inverting differential output, bidirectional control channel input. The interconnect must be AC-coupled with a 100-nF capacitor.
POWER AND GROUND
VDDPLL 10 Power, Analog PLL Power, 1.8 V ±5%
VDDT 11 Power, Analog Tx Analog Power, 1.8 V ±5%
VDDCML 14 Power, Analog CML and bidirectional channel driver power, 1.8 V ±5%
VDDD 28 Power, Digital Digital power, 1.8 V ±5%
VDDIO 25 Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
RHS Package
48-Pin WQFN
Top View
DS90UB913Q-Q1 DS90UB914Q-Q1 30144620.gif

DS90UB914Q-Q1 Deserializer Pin Functions

PIN I/O DESCRIPTION
NAME NO.
LVCMOS PARALLEL INTERFACE
ROUT[11:0] 11, 12, 13,
14, 15, 16,
18, 19, 21,
22, 23, 24		 Outputs, LVCMOS Parallel data outputs
HSYNC 10 Output, LVCMOS Horizontal SYNC output
PCLK 8 Output, LVCMOS Pixel clock output pin
Strobe edge set by RRFB control register
VSYNC 9 Output, LVCMOS Vertical SYNC output
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
GPIO[1:0] 27, 28 Digital Input/Output, LVCMOS General-purpose input/output pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPOs on the serializer or they may be configured to be outputs to follow local register settings.
GPIO[3:2] 25, 26 Digital Input/Output LVCMOS General-purpose input/output pins GPO[2:3] can be configured to be input signals for GPOs on the serializer. In addition they can also be configured to be outputs to follow the local register settings. When the SerDes chipsets are working with an external oscillator, these pins can be configured only to be outputs to follow the local register settings.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL 2 Input/Output,
Open-Drain		 Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO.
SDA 1 Input/Output,
Open-Drain		 Data line for bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO.
MODE 37 Input, LVCMOS
with pullup		 Device mode select pin
Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. The MODE pin on the deserializer can be used to configure the serializer and deserializer to work in different input PCLK range. See details in Table 8.
12-bit low-frequency mode (10- to 50-MHz operation):
In this mode, the serializer and deserializer can accept up to 12 bits DATA+2 SYNC. Input PCLK range is from 10 MHz to 50 MHz.

12-bit high-frequency mode (15- to 75-MHz operation): In this mode, the serializer and deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK range is from 15 MHz to 75 MHz.
10-bit mode (20- to 100-MHz operation):
In this mode, the serializer and deserializer can accept up to 10 bits DATA + 2 SYNC. Input PCLK frequency can range from 20 MHz to 100 MHz.
Refer to Table 4 in the Applications Information section on how to configure the MODE pin on the deserializer.
IDx[0:1] 35, 34 Input, analog The IDx[0] and IDx[1] pins on the deserializer are used to assign the I2C device address. Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. See Table 2
Input pin to select the slave device address.
Input is connect to external resistor divider to set programmable Device ID address.
CONTROL AND CONFIGURATION
PDB 30 Input, LVCMOS
with pulldown		 Power-down mode input pin
PDB = H, deserializer is enabled and is ON.
PDB = L, deserializer is in sleep (power-down mode). When the deserializer is in sleep, programmed control register data are NOT retained and reset to default values.
LOCK 48 Output,
LVCMOS		 LOCK status output pin
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as link status.
BISTEN 6 Input
LVCMOS with pulldown		 BIST enable pin
BISTEN=H, BIST mode enabled
BISTEN=L, BIST mode is disabled
PASS 47 Output,
LVCOMS		 PASS output pin for BIST mode.
PASS = H, ERROR FREE transmission
PASS = L, one or more errors were detected in the received payload.
See Built-In Self Test section for more information. Leave open if unused. Route to test point (pad) recommended.
OEN 5 Input
LVCMOS with pulldown		 Output enable input
Refer to Table 5
OSS_SEL 4 Input
LVCMOS with pulldown		 Output sleep state select pin
Refer to Table 5
SEL 46 Input
LVCMOS with pulldown		 MUX select line
SEL = L, RIN0± input. This selects input A as the active channel on the deserializer.
SEL = H, RIN1± input. This selects input B as the active channel on the deserializer.
FPD-LINK III INTERFACE
RIN0+ 41 Input/Output, CML Noninverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor
RIN0- 42 Input/Output, CML Inverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor
RIN1+ 32 Input/Output, CML Noninverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor
RIN1- 33 Input/Output, CML Inverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor
RES 43, 44 — Reserved; This pin must always be tied low.
CMLOUTP/N 38, 39 — Route to test point or leave open if unused
POWER AND GROUND
VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O buffer power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%
VDDD 17 Power, Digital Digital core power, 1.8 V ±5%
VDDSSCG 3 Power, Analog SSCG PLL power, 1.8 V ±5%
VDDR 36 Power, Analog RX analog power, 1.8 V ±5%
VDDCML0/1 40, 31 Power, Analog CML and bidirectional control channel drive power, 1.8 V±5%
VDDPLL 45 Power, Analog PLL Power, 1.8 V ±5%
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias.