SLVSAW3D July   2011  – January 2016 DRV8805

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Drivers
      2. 7.3.2 Indexer Operation
      3. 7.3.3 nENBL and RESET Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 Overcurrent Protection (OCP)
        2. 7.3.4.2 Thermal Shutdown (TSD)
        3. 7.3.4.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Step Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The DRV8805 is an integrated 4-channel unipolar stepper motor driver with a step / direction interface that controls the low-side driver outputs and allows for simple control schemes. The four low-side driver outputs consist of four N-channel MOSFETs that have a typical RDS(on) of 500 mΩ. A single motor supply input VM serves as device power and is internally regulated to power the low-side gate drive. The device outputs can be disabled by bringing the nENBL pin logic high. This device has several safety features including integrated overcurrent protection that limits the motor current to a fixed maximum above which the device will shut down. Thermal shutdown protection enables the device to automatically shut down if the die temperature exceeds a TTSD limit and will restart once the die reaches a safe temperature. UVLO protection will disable all circuitry in the device if VM drops below the undervoltage lockout threshold.

7.2 Functional Block Diagram

DRV8805 fbd_slvsaw3.gif

7.3 Feature Description

7.3.1 Output Drivers

The DRV8805 contains four protected low-side drivers. Each output has an integrated clamp diode connected to a common pin, VCLAMP.

VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a Zener or TVS diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.

In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.

7.3.2 Indexer Operation

The DRV8805 integrates an indexer to allow motor control with a simple step-and-direction interface. Logically, the indexer is shown in Figure 6.

DRV8805 fig_9_slvsaw3.gif Figure 6. Indexer Operation

7.3.3 nENBL and RESET Operation

The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.

The RESET pin, when driven active high, resets the internal logic. The indexer is reset to the home state. All inputs are ignored while RESET is active. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive RESET at power up.

7.3.4 Protection Circuits

The DRV8805 is fully protected against undervoltage, overcurrent and overtemperature events.

7.3.4.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time (approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either RESET pin is activated or VM is removed and re-applied.

7.3.4.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low. The STEP input will be ignored. Once the die temperature has fallen to a safe level, operation will automatically resume.

7.3.4.3 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold.

7.4 Device Functional Modes

7.4.1 Step Modes

The SM0 and SM1 pins select the stepping mode of the translator as shown in Table 1.

Table 1. Step Modes

SM1 SM0 MODE
0 0 2-phase drive (full step)
0 1 1-2 phase drive (half step)
1 0 1-phase excitation (wave drive)
1 1 Reserved

In all modes, during a fault condition, the STEP input will be ignored. See Protection Circuits for more information.

The sequence of the outputs is shown in Table 2, Table 3, and Table 4.

Table 2. 2-Phase Excitation (Full-Step)

Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 OUT4
Reset 1 1 X X 0 ON OFF OFF ON
CW 2 0 1 ↑ 1 ON ON OFF OFF
CW 3 0 1 ↑ 1 OFF ON ON OFF
CW 4 0 1 ↑ 1 OFF OFF ON ON
CW to home 1 0 1 ↑ 0 ON OFF OFF ON
CCW 4 0 0 ↑ 1 OFF OFF ON ON
CCW 3 0 0 ↑ 1 OFF ON ON OFF
CCW 2 0 0 ↑ 1 ON ON OFF OFF
CCW to home 1 0 0 ↑ 0 ON OFF OFF ON
Hold X 0 X ↑ no chg no chg no chg no chg no chg

Table 3. 1-2-Phase Excitation (Half-Step)

Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 OUT4
Reset 1 1 X X 0 ON OFF OFF OFF
CW 2 0 1 ↑ 1 ON ON OFF OFF
CW 3 0 1 ↑ 1 OFF ON OFF OFF
CW 4 0 1 ↑ 1 OFF ON ON OFF
CW 5 0 1 ↑ 1 OFF OFF ON OFF
CW 6 0 1 ↑ 1 OFF OFF ON ON
CW 7 0 1 ↑ 1 OFF OFF OFF ON
CW 8 0 1 ↑ 1 ON OFF OFF ON
CW to home 1 0 1 ↑ 0 ON OFF OFF OFF
CCW 8 0 0 ↑ 1 ON OFF OFF ON
CCW 7 0 0 ↑ 1 OFF OFF OFF ON
CCW 6 0 0 ↑ 1 OFF OFF ON ON
CCW 5 0 0 ↑ 1 OFF OFF ON OFF
CCW 4 0 0 ↑ 1 OFF ON ON OFF
CCW 3 0 0 ↑ 1 OFF ON OFF OFF
CCW 2 0 0 ↑ 1 ON ON OFF OFF
CCW to home 1 0 0 ↑ 0 ON OFF OFF OFF
Hold X 0 X ↑ no chg no chg no chg no chg no chg

Table 4. 1-Phase Excitation (Wave Drive)

Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 OUT4
Reset 1 1 X X 0 ON OFF OFF OFF
CW 2 0 1 ↑ 1 OFF ON OFF OFF
CW 3 0 1 ↑ 1 OFF OFF ON OFF
CW 4 0 1 ↑ 1 OFF OFF OFF ON
CW to home 1 0 1 ↑ 0 ON OFF OFF OFF
CCW 4 0 0 ↑ 1 OFF OFF OFF ON
CCW 3 0 0 ↑ 1 OFF OFF ON OFF
CCW 2 0 0 ↑ 1 OFF ON OFF OFF
CCW to home 1 0 0 ↑ 0 ON OFF OFF OFF
Hold X 0 X ↑ no chg no chg no chg no chg no chg