ZHCS218F July   2011  – December 2015 DRV8804

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Drivers
      2. 7.3.2 Serial Interface Operation
      3. 7.3.3 nENBL and RESET Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 Overcurrent Protection (OCP)
        2. 7.3.4.2 Thermal Shutdown (TSD)
        3. 7.3.4.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DW (Wide SOIC) Package
20-Pin Package
Top View
DRV8804 po_dw_lvsaw4.gif
PWP (HTSSOP)
16-Pin Package
Top View
DRV8804 po_pwp_lvsaw4.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME SOIC HTSSOP
POWER AND GROUND
GND 5, 6, 7,
14, 15, 16		 5, 12, PPAD — Device ground All pins must be connected to GND.
VM 1 1 — Device power supply Connect to motor supply (8.2 V - 60 V).
CONTROL
LATCH 13 11 I Latch input Rising edge latches shift register to output stage – internal pulldown
nENBL 10 8 I Enable input Active low enables outputs – internal pulldown
RESET 11 9 I Reset input Active-high reset input initializes internal logic – internal pulldown
SCLK 17 13 I Serial clock Serial clock input – internal pulldown
SDATIN 18 14 I Serial data input Serial data input – internal pulldown
SDATOUT 19 15 O Serial data output Serial data output; push-pull structure; see serial interface section for details
STATUS
nFAULT 20 16 OD Fault Logic low when in fault condition (overtemperature, overcurrent)
OUTPUT
OUT1 3 3 O Output 1 Connect to load 1
OUT2 4 4 O Output 2 Connect to load 2
OUT3 8 6 O Output 3 Connect to load 3
OUT4 9 7 O Output 4 Connect to load 4
VCLAMP 2 2 — Output clamp voltage Connect to VM supply, or zener diode to VM supply
(1) Directions: I = input, O = output, OD = open-drain output