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  • DRV835x 100V 三相智能栅极驱动器

    • ZHCSIN3A August   2018  – June  2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R

      PRODUCTION DATA.  

  • CONTENTS
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  • DRV835x 100V 三相智能栅极驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—32-Pin DRV8350 Devices
    2.     Pin Functions—48-Pin DRV8350R Devices
    3.     Pin Functions—40-Pin DRV8353 Devices
    4.     Pin Functions—48-Pin DRV8353R Devices
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 8.3.1.2 Device Interface Modes
          1. 8.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 8.3.1.2.2 Hardware Interface
        3. 8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
        4. 8.3.1.4 Smart Gate Drive Architecture
          1. 8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 8.3.1.4.3 Propagation Delay
          4. 8.3.1.4.4 MOSFET VDS Monitors
          5. 8.3.1.4.5 VDRAIN Sense and Reference Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
        1. 8.3.4.1 Bidirectional Current Sense Operation
        2. 8.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 8.3.4.3 Amplifier Calibration Modes
        4. 8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 8.3.5 Step-Down Buck Regulator
        1. 8.3.5.1 Functional Block Diagram
        2. 8.3.5.2 Feature Description
          1. 8.3.5.2.1 Control Circuit Overview
          2. 8.3.5.2.2 Start-Up Regulator (VCC)
          3. 8.3.5.2.3 Regulation Comparator
          4. 8.3.5.2.4 Overvoltage Comparator
          5. 8.3.5.2.5 On-Time Generator and Shutdown
          6. 8.3.5.2.6 Current Limit
          7. 8.3.5.2.7 N-Channel Buck Switch and Driver
          8. 8.3.5.2.8 Thermal Protection
      6. 8.3.6 Gate Driver Protective Circuits
        1. 8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. 8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. 8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 8.3.6.5 Gate Driver Fault (GDF)
        6. 8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
        7. 8.3.6.7 Thermal Warning (OTW)
        8. 8.3.6.8 Thermal Shutdown (OTSD)
        9. 8.3.6.9 Fault Response Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 8.4.2 Buck Regulator Functional Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Active Mode
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 SPI
          1. 8.5.1.1.1 SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. 8.6.1.1 Fault Status Register 1 (address = 0x00h)
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 8.6.1.2 Fault Status Register 2 (address = 0x01h)
          1. Table 12. Fault Status Register 2 Field Descriptions
      2. 8.6.2 Control Registers
        1. 8.6.2.1 Driver Control Register (address = 0x02h)
          1. Table 14. Driver Control Field Descriptions
        2. 8.6.2.2 Gate Drive HS Register (address = 0x03h)
          1. Table 15. Gate Drive HS Field Descriptions
        3. 8.6.2.3 Gate Drive LS Register (address = 0x04h)
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 8.6.2.4 OCP Control Register (address = 0x05h)
          1. Table 17. OCP Control Field Descriptions
        5. 8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
          1. Table 18. CSA Control Field Descriptions
        6. 8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
          1. Table 19. Driver Configuration Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External MOSFET Support
            1. 9.2.1.2.1.1 MOSFET Example
          2. 9.2.1.2.2 IDRIVE Configuration
            1. 9.2.1.2.2.1 IDRIVE Example
          3. 9.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 9.2.1.2.3.1 VDS Overcurrent Example
          4. 9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
            1. 9.2.1.2.4.1 Sense-Amplifier Example
          5. 9.2.1.2.5 Single Supply Power Dissipation
          6. 9.2.1.2.6 Single Supply Power Dissipation Example
          7. 9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Alternative Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 9.2.2.2.1.1 Sense-Amplifier Example
            2. 9.2.2.2.1.2 Dual Supply Power Dissipation
            3. 9.2.2.2.1.3 Dual Supply Power Dissipation Example
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck-Regulator Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 社区资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明

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DATA SHEET

DRV835x 100V 三相智能栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 9V 至 100V 三半桥栅极驱动器
    • 可选的集成降压稳压器
    • 可选的三个低侧电流分流放大器
  • 智能栅极驱动架构
    • 可调转换率控制，可实现优异的 EMI 性能
    • VGS 握手和最小死区时间插入，可避免发生击穿
    • 50mA 至 1A 峰值拉电流
    • 100mA 至 2A 峰值灌电流
    • 通过强下拉能力减小 dV/dt
  • 集成栅极驱动器电源
    • 高侧倍增电荷泵可实现 100% PWM 占空比控制
    • 低侧线性稳压器
  • 集成 LM5008A 降压稳压器
    • 6V 至 95V 工作电压范围
    • 2.5V 至 75V、350mA 输出能力
  • 集成三个电流分流放大器
    • 可调增益（5、10、20、40 V/V）
    • 双向或单向支持
  • 6x、3x、1x 和独立 PWM 模式
    • 支持 120° 有传感器运行
  • 提供 SPI 或硬件接口
  • 低功耗睡眠模式（VVM = 48V 时为 20µA）
  • 集成式保护 特性
    • VM 欠压锁定 (UVLO)
    • 栅极驱动电源欠压 (GDUV)
    • MOSFET VDS 过流保护 (OCP)
    • MOSFET 击穿保护
    • 栅极驱动器故障 (GDF)
    • 热警告和热关断 (OTW/OTSD)
    • 故障状态指示器 (nFAULT)

2 应用

  • 三相无刷直流 (BLDC) 电机模块
  • 风扇、风机和泵
  • 电动自行车、电动踏板车和电动汽车
  • 电动和园艺工具、割草机
  • 无人机、机器人和遥控玩具
  • 工厂自动化和纺织机

3 说明

DRV835x 系列器件均为高度集成的栅极驱动器，适用于三相无刷直流 (BLDC) 电机 应用标准。这些 应用 包括 BLDC 电机的场定向控制 (FOC)、正弦电流控制和梯形电流控制。该器件型号提供了可选的集成式分流放大器以支持不同的电机控制方案，还提供了降压稳压器，以为栅极驱动器或外部控制器供电。

DRV835x 通过采用智能栅极驱动 (SGD) 架构减少了 MOSFET 压摆率控制和保护电路通常所需要的外部组件数量。SGD 架构还可优化死区时间以防止击穿问题，在通过 MOSFET 压摆率控制技术降低电磁干扰 (EMI) 方面带来了灵活性，并可通过 VGS 监控器防止栅极短路问题。强大的栅极下拉电路有助于防止不必要的 dV/dt 寄生栅极开启事件。

该系列器件支持各种 PWM 控制模式（6x、3x、1x 和独立模式），可简化与外部控制器的连接。这些模式可减少电机驱动器 PWM 控制信号所需的控制器输出数量。该系列器件还包括 1x PWM 模式，因此可通过内部阻塞换向表轻松对 BLDC 电机进行传感器式梯形控制。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
DRV8350 WQFN (32) 5.00mm × 5.00mm
DRV8350R VQFN (48) 7.00mm × 7.00mm
DRV8353 WQFN (40) 6.00mm × 6.00mm
DRV8353R VQFN (48) 7.00mm × 7.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简化原理图

DRV8350 DRV8350R DRV8353 DRV8353R drv835x-simp-sch.gif

4 修订历史记录

Changes from * Revision (August 2018) to A Revision

  • Changed 将文档状态更改为生产数据Go
  • Deleted 从 DRV8350 和 DRV8353 器件中删除了仅供预览的标注Go

5 Device Comparison Table

DEVICE VARIANT SHUNT AMPLIFIERS BUCK REGULATOR INTERFACE
DRV8350 DRV8350H 0 None Hardware (H)
DRV8350S SPI (S)
DRV8350R DRV8350RH 350 mA (R) Hardware (H)
DRV8350RS SPI (S)
DRV8353 DRV8353H 3 None Hardware (H)
DRV8353S SPI (S)
DRV8353R DRV8353RH 350 mA (R) Hardware (H)
DRV8353RS SPI (S)

6 Pin Configuration and Functions

DRV8350H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
DRV8350S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View

Pin Functions—32-Pin DRV8350 Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8350H DRV8350S
CPH 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 32 32 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DVDD 29 29 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally.
ENABLE 22 22 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used to reset fault conditions.
GHA 5 5 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 12 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 13 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 7 7 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 30 30 PWR Device primary ground. Connect to system ground.
IDRIVE 19 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 23 23 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 25 25 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 27 27 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 24 24 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 21 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source.
VCP 4 4 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 3 3 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 31 31 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM 2 2 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8350RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8350RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions—48-Pin DRV8350R Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8350RH DRV8350RS
AGND 27 27 PWR Device analog ground. Connect to system ground.
BST 45 45 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DGND 41 41 PWR Device digital ground. Connect to system ground.
DVDD 40 40 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally.
ENABLE 33 33 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 48 48 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 1 1 PWR Device primary ground. Connect to system ground.
IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 12 12 NC No internal connection. This pin can be left floating or connected to system ground.
NC 13 13 NC No internal connection. This pin can be left floating or connected to system ground.
NC 22 22 NC No internal connection. This pin can be left floating or connected to system ground.
NC 23 23 NC No internal connection. This pin can be left floating or connected to system ground.
NC 24 24 NC No internal connection. This pin can be left floating or connected to system ground.
NC 25 25 NC No internal connection. This pin can be left floating or connected to system ground.
NC 26 26 NC No internal connection. This pin can be left floating or connected to system ground.
NC 32 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.
RCL 46 46 I Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD 47 47 I On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 11 11 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 14 14 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 21 21 I Low-side source sense input. Connect to the low-side power MOSFET source.
SW 42 42 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC 44 44 PWR 7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins.
VCP 7 7 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 6 6 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 2 2 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN 43 43 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
VM 5 5 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8353H RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
DRV8353S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View

Pin Functions—40-Pin DRV8353 Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8353H DRV8353S
AGND 25 25 PWR Device analog ground. Connect to system ground.
CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DVDD 38 38 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally.
ENABLE 31 31 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
GAIN 30 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 39 39 PWR Device power ground. Connect to system ground.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 28 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 27 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 26 26 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 30 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 29 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 28 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 27 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Shunt amplifier output.
SOB 22 22 O Shunt amplifier output.
SOC 21 21 O Shunt amplifier output.
SPA 9 9 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 12 12 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 19 19 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 4 4 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 29 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 40 40 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM 3 3 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF 24 24 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
DRV8353RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
DRV8353RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions—48-Pin DRV8353R Devices

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8353RH DRV8353RS
AGND 27 27 PWR Device analog ground. Connect to system ground.
BST 45 45 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DGND 41 41 PWR Device ground. Connect to system ground.
DVDD 40 40 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally.
ENABLE 33 33 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
FB 48 48 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GAIN 32 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 1 1 PWR Device power ground. Connect to system ground.
GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication.
RCL 46 46 I Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD 47 47 I On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 12 12 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 13 13 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 22 22 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 25 25 O Shunt amplifier output.
SOB 24 24 O Shunt amplifier output.
SOC 23 23 O Shunt amplifier output.
SPA 11 11 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 14 14 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 21 21 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SW 42 42 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC 44 44 PWR 7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins.
VCP 7 7 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 6 6 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 2 2 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN 43 43 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM 5 5 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF 26 26 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain

7 Specifications

7.1 Absolute Maximum Ratings

at TA = –40°C to +125°C (unless otherwise noted)(1)
MIN MAX UNIT
GATE DRIVER
Power supply pin voltage (VM) –0.3 80 V
Voltage differential between ground pins (AGND, BGND, DGND, PGND) –0.3 0.3 V
MOSFET drain sense pin voltage (VDRAIN) –0.3 102 V
MOSFET drain sense pin voltage slew rate (VDRAIN) 0 2 V/µs
Charge pump pin voltage (CPH, VCP) –0.3 VVDRAIN + 16 V
Charge-pump negative-switching pin voltage (CPL) –0.3 VVDRAIN V
Low-side gate drive regulator pin voltage (VGLS) –0.3 18 V
Internal logic regulator pin voltage (DVDD) –0.3 5.75 V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) –0.3 5.75 V
Continuous high-side gate drive pin voltage (GHx) –5(2) VVCP + 0.3 V
Transient 200-ns high-side gate drive pin voltage (GHx) –10 VVCP + 0.3 V
High-side gate drive pin voltage with respect to SHx (GHx) –0.3 16 V
Continuous high-side source sense pin voltage (SHx) –5(2) 102 V
Continuous high-side source sense pin voltage (SHx) –5(2) VVDRAIN + 5 V
Transient 200-ns high-side source sense pin voltage (SHx) –10 VVDRAIN + 10 V
Continuous low-side gate drive pin voltage (GLx) –1.0 VVGLS + 0.3 V
Transient 200-ns low-side gate drive pin voltage (GLx) –5.0 VVGLS + 0.3 V
Gate drive pin source current (GHx, GLx) Internally limited Internally limited A
Gate drive pin sink current (GHx, GLx) Internally limited Internally limited A
Continuous low-side source sense pin voltage (SLx) –1 1 V
Transient 200-ns low-side source sense pin voltage (SLx) –5 5 V
Continuous shunt amplifier input pin voltage (SNx, SPx) –1 1 V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx) –5 5 V
Reference input pin voltage (VREF) –0.3 5.75 V
Shunt amplifier output pin voltage (SOx) –0.3 VVREF + 0.3 V
BUCK REGULATOR
Power supply pin voltage (VIN) –0.3 100 V
Bootstrap pin voltage (BST) –0.3 114 V
Bootstrap pin voltage with respect to SW (BST) –0.3 14 V
Bootstrap pin voltage with respect to VCC (BST) –0.3 100 V
Switching node pin voltage (SW) –1 VVIN V
Internal regulator pin voltage (VCC) –0.3 14 V
Input pin voltage (FB, RCL, RT/SD) –0.3 7 V
DRV835x
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum. This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

7.3 Recommended Operating Conditions

at TA = –40°C to +125°C (unless otherwise noted)
MIN MAX UNIT
GATE DRIVER
VVM Gate driver power supply voltage (VM) 9 75 V
VVDRAIN Charge pump reference and drain voltage sense (VDRAIN) 7 100 V
VI Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) 0 5.5 V
fPWM Applied PWM signal (INHx, INLx) 0 200(1) kHz
tSH Switch-node slew rate range (SHx) 0 2 V/ns
IGATE_HS High-side average gate-drive current (GHx) 0 25(1) mA
IGATE_LS Low-side average gate-drive current (GLx) 0 25(1) mA
IDVDD External load current (DVDD) 0 10(1) mA
VVREF Reference voltage input (VREF) 3 5.5 V
ISO Shunt amplifier output current (SOx) 0 5 mA
VOD Open drain pullup voltage (nFAULT, SDO) 0 5.5 V
IOD Open drain output current (nFAULT, SDO) 0 5 mA
BUCK REGULATOR
VVIN Power supply voltage (VIN) 6 95 V
DRV835x
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C
(1) Power dissipation and thermal limits must be observed.

7.4 Thermal Information

THERMAL METRIC(1) DRV8350 DRV8353 DRV835xR UNIT
RTV (WQFN) RTA (WQFN) RGZ (VQFN)
32 PINS 40 PINS 48 PINS
RθJA Junction-to-ambient thermal resistance 29.2 26.1 24.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.2 13.1 12.0 °C/W
RθJB Junction-to-board thermal resistance 9.2 8.4 7.1 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.1 0.1 °C/W
ψJB Junction-to-board characterization parameter 9.2 8.4 7.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.1 0.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM VM operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 8.5 13 mA
IVDRAIN VDRAIN operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 1.9 4 mA
ISLEEP Sleep mode supply current ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C 20 40 µA
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C 100
tRST Reset pulse time ENABLE = 0 V period to reset faults 5 40 µs
tWAKE Turnon time VVM > VUVLO, ENABLE = 3.3 V to outputs ready 1 ms
tSLEEP Turnoff time ENABLE = 0 V to device sleep mode 1 ms
VDVDD DVDD regulator voltage IDVDD = 0 to 10 mA 4.75 5 5.25 V
VVCP VCP operating voltage
with respect to VDRAIN		 VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12 V
VVM = 12 V, IVCP = 0 to 20 mA 7.5 10 11.5
VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5
VVGLS VGLS operating voltage
with respect to GND		 VVM = 15 V, IVGLS = 0 to 25 mA 13 14.5 16 V
VVM = 12 V, IVGLS = 0 to 20 mA 10 11.5 12.5
VVM = 10 V, IVGLS = 0 to 15 mA 8 9.5 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 7 8.5 9.5
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL Input logic low voltage 0 0.8 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VVIN = 0 V –5 5 µA
IIH Input logic high current VVIN = 5 V 50 70 µA
RPD Pulldown resistance To GND 100 kΩ
tPD Propagation delay INHx/INLx transition to GHx/GLx transition 200 ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1 Input mode 1 voltage Tied to GND 0 V
VI2 Input mode 2 voltage 47 kΩ ± 5% to tied GND 1.9 V
VI3 Input mode 3 voltage Hi-Z 3.1 V
VI4 Input mode 4 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 50 kΩ
RPD Pulldown resistance Internal pulldown to GND 84 kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to GND 0 V
VI2 Input mode 2 voltage 18 kΩ ± 5% tied to GND 0.8 V
VI3 Input mode 3 voltage 75 kΩ ± 5% tied to GND 1.7 V
VI4 Input mode 4 voltage Hi-Z 2.5 V
VI5 Input mode 5 voltage 75 kΩ ± 5% tied to DVDD 3.3 V
VI6 Input mode 6 voltage 18 kΩ ± 5% tied to DVDD 4.2 V
VI7 Input mode 7 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 73 kΩ
RPD Pulldown resistance Internal pulldown to GND 73 kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL Output logic low voltage IO = 5 mA 0.125 V
IOZ Output high impedance leakage VO = 5 V –2 2 µA
GATE DRIVERS (GHx, GLx)
VGSH High-side gate drive voltage
with respect to SHx		 VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12 V
VVM = 12 , IVCP = 0 to 20 mA 7.5 10 11.5
VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5
VGSL Low-side gate drive voltage
with respect to PGND		 VVM = 15 V, IVGLS = 0 to 25 mA 9.5 11 12.5 V
VVM = 12 V, IVGLS = 0 to 20 mA 9 10.5 12
VVM = 10 V, IVGLS = 0 to 15 mA 7.5 9 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 6.5 8 9.5
tDEAD Gate drive
dead time		 SPI Device DEAD_TIME = 00b 50 ns
DEAD_TIME = 01b 100
DEAD_TIME = 10b 200
DEAD_TIME = 11b 400
H/W Device 100
tDRIVE Peak current
gate drive time		 SPI Device TDRIVE = 00b 500 ns
TDRIVE = 01b 1000
TDRIVE = 10b 2000
TDRIVE = 11b 4000
H/W Device 4000
IDRIVEP Peak source
gate current		 SPI Device IDRIVEP_HS or IDRIVEP_LS = 0000b 50 mA
IDRIVEP_HS or IDRIVEP_LS = 0001b 50
IDRIVEP_HS or IDRIVEP_LS = 0010b 100
IDRIVEP_HS or IDRIVEP_LS = 0011b 150
IDRIVEP_HS or IDRIVEP_LS = 0100b 300
IDRIVEP_HS or IDRIVEP_LS = 0101b 350
IDRIVEP_HS or IDRIVEP_LS = 0110b 400
IDRIVEP_HS or IDRIVEP_LS = 0111b 450
IDRIVEP_HS or IDRIVEP_LS = 1000b 550
IDRIVEP_HS or IDRIVEP_LS = 1001b 600
IDRIVEP_HS or IDRIVEP_LS = 1010b 650
IDRIVEP_HS or IDRIVEP_LS = 1011b 700
IDRIVEP_HS or IDRIVEP_LS = 1100b 850
IDRIVEP_HS or IDRIVEP_LS = 1101b 900
IDRIVEP_HS or IDRIVEP_LS = 1110b 950
IDRIVEP_HS or IDRIVEP_LS = 1111b 1000
H/W Device IDRIVE = Tied to GND 50
IDRIVE = 18 kΩ ± 5% tied to GND 100
IDRIVE = 75 kΩ ± 5% tied to GND 150
IDRIVE = Hi-Z 300
IDRIVE = 75 kΩ ± 5% tied to DVDD 450
IDRIVE = 18 kΩ ± 5% tied to DVDD 700
IDRIVE = Tied to DVDD 1000
IDRIVEN Peak sink
gate current		 SPI Device IDRIVEN_HS or IDRIVEN_LS = 0000b 100 mA
IDRIVEN_HS or IDRIVEN_LS = 0001b 100
IDRIVEN_HS or IDRIVEN_LS = 0010b 200
IDRIVEN_HS or IDRIVEN_LS = 0011b 300
IDRIVEN_HS or IDRIVEN_LS = 0100b 600
IDRIVEN_HS or IDRIVEN_LS = 0101b 700
IDRIVEN_HS or IDRIVEN_LS = 0110b 800
IDRIVEN_HS or IDRIVEN_LS = 0111b 900
IDRIVEN_HS or IDRIVEN_LS = 1000b 1100
IDRIVEN_HS or IDRIVEN_LS = 1001b 1200
IDRIVEN_HS or IDRIVEN_LS = 1010b 1300
IDRIVEN_HS or IDRIVEN_LS = 1011b 1400
IDRIVEN_HS or IDRIVEN_LS = 1100b 1700
IDRIVEN_HS or IDRIVEN_LS = 1101b 1800
IDRIVEN_HS or IDRIVEN_LS = 1110b 1900
IDRIVEN_HS or IDRIVEN_LS = 1111b 2000
H/W Device IDRIVE = Tied to GND 100
IDRIVE = 18 kΩ ± 5% tied to GND 200
IDRIVE = 75 kΩ ± 5% tied to GND 300
IDRIVE = Hi-Z 600
IDRIVE = 75 kΩ ± 5% tied to DVDD 900
IDRIVE = 18 kΩ ± 5% tied to DVDD 1400
IDRIVE = Tied to DVDD 2000
IHOLD Gate holding current Source current after tDRIVE 50 mA
Sink current after tDRIVE 100
ISTRONG Gate strong pulldown current GHx to SHx and GLx to SPx/SLx 2 A
ROFF Gate hold off resistor GHx to SHx and GLx to SPx/SLx 150 kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
GCSA Amplifier gain SPI Device CSA_GAIN = 00b 4.85 5 5.15 V/V
CSA_GAIN = 01b 9.7 10 10.3
CSA_GAIN = 10b 19.4 20 20.6
CSA_GAIN = 11b 38.8 40 41.2
H/W Device GAIN = Tied to GND 4.85 5 5.15
GAIN = 47 kΩ ± 5% tied to GND 9.7 10 10.3
GAIN = Hi-Z 19.4 20 20.6
GAIN = Tied to DVDD 38.8 40 41.2
tSET Settling time to ±1% VO_STEP = 0.5 V, GCSA = 5 V/V 250 ns
VO_STEP = 0.5 V, GCSA = 10 V/V 500
VO_STEP = 0.5 V, GVSA = 20 V/V 1000
VO_STEP = 0.5 V, GCSA = 40 V/V 2000
VCOM Common mode input range –0.15 0.15 V
VDIFF Differential mode input range –0.3 0.3 V
VOFF Input offset error VSP = VSN = 0 V –3 3 mV
VDRIFT Drift offset VSP = VSN = 0 V 10 µV/°C
VLINEAR SOx output voltage linear range 0.25 VVREF – 0.25 V
VBIAS SOx output voltage bias SPI Device VSP = VSN = 0 V, VREF_DIV = 0b VVREF – 0.3 V
VSP = VSN = 0 V, VREF_DIV = 1b VVREF / 2
H/W Device VSP = VSN = 0 V VVREF / 2
IBIAS SPx/SNx input bias current 250 µA
VSLEW SOx output slew rate 60-pF load 10 V/µs
IVREF VREF input current VVREF = 5 V 1.5 2.5 mA
UGB Unity gain bandwidth DRV835x: 60-pF load 10 MHz
DRV835xR: 60-pF load 1 MHz
PROTECTION CIRCUITS
VVM_UV VM undervoltage lockout DRV835x: VM falling, UVLO report 8.0 8.3 8.8 V
DRV835x: VM rising, UVLO recovery 8.2 8.5 9.0
DRV835xR: VM falling, UVLO report 8.0 8.3 8.6
DRV835xR: VM rising, UVLO recovery 8.2 8.5 8.8
VVM_UVH VM undervoltage hysteresis Rising to falling threshold 200 mV
tVM_UVD VM undervoltage deglitch time VM falling, UVLO report 10 µs
VVDR_UV VDRAIN undervoltage lockout DRV835x: VDRAIN falling, UVLO report 6.1 6.4 6.8 V
DRV835x: VDRAIN rising, UVLO recovery 6.3 6.6 7.0
DRV835xR: VDRAIN falling, UVLO report 6.1 6.4 6.7
DRV835xR: VDRAIN rising, UVLO recovery 6.3 6.6 6.9
VVDR_UVH VDRAIN undervoltage hysteresis Rising to falling threshold 200 mV
tVDR_UVD VDRAIN undervoltage deglitch time VDRAIN falling, UVLO report 10 µs
VVCP_UV VCP charge pump undervoltage lockout VCP falling, GDUV report VDRAIN + 5 V
VVGLS_UV VGLS low-side regulator undervoltage lockout VGLS falling, GDUV report 4.25 V
VGS_CLAMP High-side gate clamp Positive clamping voltage 12.5 13.5 16 V
Negative clamping voltage –0.7
VVDS_OCP VDS overcurrent
trip voltage		 SPI Device DRV835x: VDS_LVL = 0000b 0.041 0.06 0.072 V
DRV835x: VDS_LVL = 0001b 0.051 0.07 0.084
DRV835x: VDS_LVL = 0010b 0.061 0.08 0.096
DRV835x: VDS_LVL = 0011b 0.071 0.09 0.108
DRV835x: VDS_LVL = 0100b 0.081 0.1 0.115
DRV835xR: VDS_LVL = 0000b 0.048 0.06 0.072
DRV835xR: VDS_LVL = 0001b 0.056 0.07 0.084
DRV835xR: VDS_LVL = 0010b 0.064 0.08 0.096
DRV835xR: VDS_LVL = 0011b 0.072 0.09 0.108
DRV835xR: VDS_LVL = 0100b 0.085 0.1 0.115
VDS_LVL = 0101b 0.18 0.2 0.22
VDS_LVL = 0110b 0.27 0.3 0.33
VDS_LVL = 0111b 0.36 0.4 0.44
VDS_LVL = 1000b 0.45 0.5 0.55
VDS_LVL = 1001b 0.54 0.6 0.66
VDS_LVL = 1010b 0.63 0.7 0.77
VDS_LVL = 1011b 0.72 0.8 0.88
VDS_LVL = 1100b 0.81 0.9 0.99
VDS_LVL = 1101b 0.9 1.0 1.1
VDS_LVL = 1110b 1.35 1.5 1.65
VDS_LVL = 1111b 1.8 2 2.2
H/W Device DRV835x: VDS = Tied to GND 0.041 0.06 0.072 V
DRV835x: VDS = 18 kΩ ± 5% tied to GND 0.081 0.1 0.115
DRV835xR: VDS = Tied to GND 0.048 0.06 0.072
DRV835xR: VDS = 18 kΩ ± 5% tied to GND 0.085 0.1 0.115
VDS = 75 kΩ ± 5% tied to GND 0.18 0.2 0.22
VDS = Hi-Z 0.36 0.4 0.44
VDS = 75 kΩ ± 5% tied to DVDD 0.63 0.7 0.77
VDS = 18 kΩ ± 5% tied to DVDD 0.9 1 1.1
VDS = Tied to DVDD Disabled
tOCP_DEG VDS and VSENSE overcurrent deglitch time SPI Device OCP_DEG = 00b 1 µs
OCP_DEG = 01b 2
OCP_DEG = 10b 4
OCP_DEG = 11b 8
H/W Device 4
VSEN_OCP VSENSE overcurrent trip voltage SPI Device SEN_LVL = 00b 0.25 V
SEN_LVL = 01b 0.5
SEN_LVL = 10b 0.75
SEN_LVL = 11b 1
H/W Device 1
tRETRY Overcurrent retry time SPI Device TRETRY = 0b 8 ms
TRETRY = 1b 50 μs
H/W Device 8 ms
TOTW Thermal warning temperature Die temperature, TJ 130 150 170 °C
TOTSD Thermal shutdown temperature Die temperature, TJ 150 170 190 °C
THYS Thermal hysteresis Die temperature, TJ 20 °C
BUCK REGULATOR VCC
VVCC_REG VCC regulator voltage 6.6 7 7.4 V
VVIN = 6 to 8.5 V 100 mV
VVCC_BYT VCC bypass threshold VVIN increasing 8.5 V
VVCC_BYH VCC bypass hysteresis 300 mV
VVCC_OUT VCC output impedance VVIN = 6 V 100 Ω
VVIN = 10 V 8.8 Ω
VVIN = 48 V 0.8 Ω
VVCC_LIM VCC current limit 9.2 mA
VVCC_UV VCC undervoltage lockout 5.3 V
VVCC_UVH VCC undervoltage lockout hysteresis 190 mV
VVCC_UVFD VCC filter delay 3 μs
IIN_OP IIN operating current FB = 3 V 550 750 μA
IIN_OP IIN shutdown current RT/SD = 0 V 110 176 μA
BUCK REGULATOR SWITCHING
RDS(on) Buck switch RDS(on) ITEST = 200 mA 1.25 2.57 Ω
VGATE_UV Gate drive undervoltage lockout VBST - VSW rising 2.8 3.8 4.8 V
VGATE_UVH Gate drive undervoltage lockout hysteresis 490 mV
VSWITCH Pre-charge switch voltage At 1 mA 0.8 V
tON Pre-charge switch on-time 150 ns
BUCK REGULATOR CURRENT LIMIT
ILIMIT Current limit threshold 0.41 0.51 0.61 A
tLIM Current limit response time ISW overdrive = 0.1 A, time to switch off 350 ns
tOFF1 Off time generator FB = 0 V, RCL = 100 kΩ 35 μs
tOFF2 Off time generator FB = 2.3 V, RCL = 100 kΩ 2.56 μs
BUCK REGULATOR ON TIME GENERATOR
tON1 Ton 1 VVIN = 10 V, RON = 200 kΩ 2.15 2.77 3.5 μs
tON2 Ton 2 VVIN = 95 V, RON = 200 kΩ 200 300 420 μs
VSDT Remote shutdown threshold Rising 0.4 0.7 1.05 V
VSDH Remote shutdown hysteresis 35 mV
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MIN Minimum off time FB = 0 V 300 ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFB FB reference threshold Internal reference, trip point for switch on 2.445 2.5 2.55 V
VFB_OV FB overvoltage threshold Trip point for switch off 2.875 V
IFB_BIAS FB bias current 100 μA
BUCK REGULATOR THERMAL SHUTDOWN
TSD Thermal shutdown threshold 165 °C
TSDH Thermal shutdown hysteresis 25 °C

7.6 SPI Timing Requirements

at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)
MIN NOM MAX UNIT
tREADY SPI ready after enable VM > UVLO, ENABLE = 3.3 V 1 ms
tCLK SCLK minimum period 100 ns
tCLKH SCLK minimum high time 50 ns
tCLKL SCLK minimum low time 50 ns
tSU_SDI SDI input data setup time 20 ns
tH_SDI SDI input data hold time 30 ns
tD_SDO SDO output data delay time SCLK high to SDO valid 30 ns
tSU_nSCS nSCS input setup time 50 ns
tH_nSCS nSCS input hold time 50 ns
tHI_nSCS nSCS minimum high time before active low 400 ns
tDIS_nSCS nSCS disable time nSCS high to SDO high impedance 10 ns
DRV8350 DRV8350R DRV8353 DRV8353R td_spi_slave_slvsdj3.gifFigure 1. SPI Slave Mode Timing Diagram

7.7 Typical Characteristics

DRV8350 DRV8350R DRV8353 DRV8353R D001_SLVSDY6.gif
VVM = VVDRAIN
Figure 2. VM Supply Current Over Supply Voltage
DRV8350 DRV8350R DRV8353 DRV8353R D003_SLVSDY6.gif
IVM + IVDRAIN
Figure 4. Sleep Current Over Supply Voltage
DRV8350 DRV8350R DRV8353 DRV8353R D005_SLVSDY6.gif
VVM = 48-V
Figure 6. VCP Voltage Over Load
DRV8350 DRV8350R DRV8353 DRV8353R D007_SLVSDY6.gif
VVM = 15-V
Figure 8. VCP Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D009_SLVSDY6.gif
VVM = 12-V
Figure 10. VCP Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D011_SLVSDY6.gif
VVM = 9-V
Figure 12. VCP Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D002_SLVSDY6.gif
VVM = VVDRAIN
Figure 3. VDRAIN Supply Current Over Supply Voltage
DRV8350 DRV8350R DRV8353 DRV8353R D004_SLVSDY6.gif
IVM + IVDRAIN
Figure 5. Sleep Current Over Temperature
DRV8350 DRV8350R DRV8353 DRV8353R D006_SLVSDY6.gif
VVM = 48-V
Figure 7. VGLS Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D008_SLVSDY6.gif
VVM = 15-V
Figure 9. VGLS Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D010_SLVSDY6.gif
VVM = 12-V
Figure 11. VGLS Voltage Over Load Current
DRV8350 DRV8350R DRV8353 DRV8353R D012_SLVSDY6.gif
VVM = 9-V
Figure 13. VGLS Voltage Over Load Current

 
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