ZHCSP68C December   2021  – October 2022 DRV8328

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.5.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.5.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.5.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3 Gate Drive Current
          4. 9.2.1.1.4 Gate Resistor Selection
          5. 9.2.1.1.5 System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6 Dead Time Resistor Selection
          7. 9.2.1.1.7 VDSLVL Selection
          8. 9.2.1.1.8 AVDD Power Losses
          9. 9.2.1.1.9 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 说明

DRV8328 系列器件是适用于三相应用的集成栅极驱动器。这类器件具有三个半桥栅极驱动器，每个驱动器都能够驱动高侧和低侧 N 沟道功率 MOSFET。该器件使用内部电荷泵生成合适的栅极驱动电压，使用自举电路增强高侧 MOSFET。具有涓流电荷泵，支持 100% 占空比。此栅极驱动架构支持高达 1A 的峰值栅极驱动拉电流和 2A 的峰值栅极驱动灌电流。DRV8328 由单一电源供电，支持 4.5V 至 60V 的宽输入电源电压范围。

6x 和 3x PWM 模式可简化与控制器电路的连接。该器件具有集成的精密 3.3V LDO，该 LDO 可用于为外部控制器供电，并可用作 CSA 的基准电压。器件的配置设置可通过硬件 (H/W) 引脚来配置。

提供低功耗休眠模式，可通过关断大部分内部电路实现低静态电流。针对欠压锁定、GVDD 故障、MOSFET 过流、MOSFET 短路和过热等情况，提供内部保护功能。在 nFAULT 引脚上指示故障条件。

器件信息(1)
器件型号封装封装尺寸（标称值）
DRV8328ARUYWQFN (28)4.00mm × 4.00mm
DRV8328BRUYWQFN (28)4.00mm × 4.00mm
DRV8328CRUYWQFN (28)4.00mm × 4.00mm
DRV8328DRUYWQFN (28)4.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
DRV8328 简化版原理图