ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
When DRVOFF is driven high, the gate driver goes into shutdown, overriding signals on inputs pins INHx and INLx. DRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver output (see Figure 8-8). This pin provides a mechanism for externally monitored faults to disable the gate driver by directly bypassing an external controller or the internal control logic. When the DRV8328 detects that the DRVOFF pin is driven high, it disables the gate driver and puts it into pulldown mode (see Figure 8-9). The gate driver shutdown sequence proceeds as shown in Figure 8-9. When the gate driver initiates the shutdown sequence, the active driver pulldown is applied at ISINK current for the tSD_SINK_DIG time, after which the gate driver moves to passive pulldown mode.