ZHCS244C January   2012  – August 2015 DLPC300

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Crystal Port Electrical Characteristics
    7. 6.7  Power Consumption
    8. 6.8  I2C Interface Timing Requirements
    9. 6.9  Parallel Interface Frame Timing Requirements
    10. 6.10 Parallel Interface General Timing Requirements
    11. 6.11 Parallel I/F Maximum Supported Horizontal Line Rate
    12. 6.12 BT.565 I/F General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 Mobile Dual Data Rate (mDDR) Memory Interface Timing Requirements
    16. 6.16 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Control
      2. 7.4.2 Parallel Bus Interface
      3. 7.4.3 BT.656 Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 System Input Interfaces
          1. 8.2.2.1.1 Control Interface
        2. 8.2.2.2 Input Data Interface
        3. 8.2.2.3 System Output Interfaces
          1. 8.2.2.3.1 Illumination Interface
        4. 8.2.2.4 System Support Interfaces
          1. 8.2.2.4.1 Mobile DDR Synchronous Dram (MDDR)
          2. 8.2.2.4.2 Flash Memory Interface
          3. 8.2.2.4.3 DLPC300 Reference Clock
        5. 8.2.2.5 DMD Interfaces
          1. 8.2.2.5.1 DLPC300 to DLP3000 Digital Data
          2. 8.2.2.5.2 DLPC300 to DLP3000 Control Interface
          3. 8.2.2.5.3 DLPC300 to DLP3000 Micromirror Reset Control Interface
        6. 8.2.2.6 Maximum Signal Transition Time
    3. 8.3 System Examples
      1. 8.3.1 Video Source System Application
      2. 8.3.2 High Pattern Rate System With Optional Fpga
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-Up and Power-Down Sequence
      1. 9.1.1 Power Up Sequence
      2. 9.1.2 Power Down Sequence
      3. 9.1.3 Additional Power-Up Initialization Sequence Details
    2. 9.2 System Power I/O State Considerations
    3. 9.3 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Printed Circuit Board Design Guidelines
      2. 10.1.2 Printed Circuit Board Layer Stackup Geometry
      3. 10.1.3 Signal Layers
      4. 10.1.4 Routing Constraints
      5. 10.1.5 Termination Requirements
      6. 10.1.6 PLL
      7. 10.1.7 General Handling Guidelines for Unused CMOS-Type Pins
      8. 10.1.8 Hot-Plug Usage
      9. 10.1.9 External Clock Input Crystal Oscillator
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 器件命名规则
      3. 11.1.3 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZVB|176
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

ZVB Package
176-Pin NFBGA
Bottom View
DLPC300 po_bot_LPS023.gif

Pin Functions

PIN I/O
POWER		 I/O
TYPE		 CLK SYSTEM DESCRIPTION
NAME NO.
SIGNALS
RESET J14 VCC18 I1 Async

DLPC300 power-on reset. Self configuration starts when a low-to-high transition is detected on this pin. All device power and clocks must be stable and within recommended operating conditions before this reset is deasserted. Note that the following 7 signals are high-impedance while RESET is asserted:

DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0

External pullups/pulldowns should be added as needed to these signals to avoid floating inputs where these signals are driven.
PARK B8 VCC_ INTF I3 Async DMD park control (active-low). Is set high to enable normal operation. PARK must be set high within 500 µs after releasing RESET. PARK must be set low a minimum of 500 µs before any power is to be removed from the DLPC300 or DLP3000. See System Power-Up/Power-Down Sequence for more details.
PLL_REFCLK_I K15 VCC18 (filter) I4 N/A Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin should be used as the oscillator input.
PLL_REFCLK_O J15 VCC18 (filter) O14 N/A Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin should be left unconnected (floating).
FLASH INTERFACE(1)
SPICLK A4 VCC_FLSH O24 N/A SPI master clock output
SPIDIN B4 VCC_FLSH I2 SPICLK Serial data input from the external SPI slave FLASH device
SPICS0 A5 VCC_FLSH O24 SPICLK SPI master chip select 0 output. Active-low
RESERVED C6 VCC_FLSH O24 SPICLK Not used. Reserved for future use. Should be left unconnected
SPIDOUT C5 VCC_FLSH O24 SPICLK Serial data output to the external SPI slave flash device. This pin sends address and control information as well as data when programming.
CONTROL
SCL A10 VCC_ INTF B38 N/A

I2C clock. Bidirectional, open-drain signal. An external pullup is required. No I2C activity is permitted for a minimum of 100 ms after PARK and RESET are set high.
SDA C10 VCC_ INTF B38 SCL

I2C data. Bidirectional, open-drain signal. An external pullup is required.
INIT_DONE C9 VCC_ INTF B34 Async

Primary usage is to indicate when auto-initialization is complete, which is when INIT_DONE transitions high then low following release of RESET. INIT_DONE also helps flag a detected error condition in the form of a logic-high, pulsed interrupt flag.

PARALLEL RGB INTERFACE PARALLEL RGB MODE BT.656 I/F MODE
PCLK D13 VCC_ INTF I3 N/A Pixel clock(5) Pixel clock(5)
PDM H15 VCC_ INTF B34 ASYNC Not used, pulldown through an external resistor. Not used, pulldown through an external resistor.
VSYNC H14 VCC_ INTF I3 ASYNC VSync(4) Unused(3)
HSYNC H13 VCC_ INTF I3 PCLK HSync(4) Unused(3)
DATEN G15 VCC_ INTF I3 PCLK Data valid(5) Unused(3)
PDATA[0] G14 VCC_ INTF I3 PCLK Data0(2) Data0(2)
PDATA[1] G13 VCC_ INTF I3 PCLK Data1(2) Data1(2)
PDATA[2] F15 VCC_ INTF I3 PCLK Data2(2) Data2(2)
PDATA[3] F14 VCC_ INTF I3 PCLK Data3(2) Data3(2)
PDATA[4] F13 VCC_ INTF I3 PCLK Data4(2) Data4(2)
PDATA[5] E15 VCC_ INTF I3 PCLK Data5(2) Data5(2)
PDATA[6] E14 VCC_ INTF I3 PCLK Data6(2) Data6(2)
PDATA[7] E13 VCC_ INTF I3 PCLK Data7(2) Data7(2)
PDATA[8] D15 VCC_ INTF I3 PCLK Data8(2) Unused(3)
PDATA[9] D14 VCC_ INTF I3 PCLK Data9(2) Unused(3)
PDATA[10] C15 VCC_ INTF I3 PCLK Data10(2) Unused(3)
PDATA[11] C14 VCC_ INTF I3 PCLK Data11(2) Unused(3)
PDATA[12] C13 VCC_ INTF I3 PCLK Data12(2) Unused(3)
PDATA[13] B15 VCC_ INTF I3 PCLK Data13(2) Unused(3)
PDATA[14] B14 VCC_ INTF I3 PCLK Data14(2) Unused(3)
PDATA[15] A15 VCC_ INTF I3 PCLK Data15(2) Unused(3)
PDATA[16] A14 VCC_ INTF I3 PCLK Data16(2) Unused(3)
PDATA[17] B13 VCC_ INTF I3 PCLK Data17(2) Unused(3)
PDATA[18] A13 VCC_ INTF I3 PCLK Data18(2) Unused(3)
PDATA[19] C12 VCC_ INTF I3 PCLK Data19(2) Unused(3)
PDATA[20] B12 VCC_ INTF I3 PCLK Data20(2) Unused(3)
PDATA[21] A12 VCC_ INTF I3 PCLK Data21(2) Unused(3)
PDATA[22] C11 VCC_ INTF I3 PCLK Data22(2) Unused(3)
PDATA[23] B11 VCC_ INTF I3 PCLK Data23(2) Unused(3)
DMD INTERFACE
DMD_D0 M15 VCC18 O58 DMD_DCLK

DMD data pins. DMD data pins are double data rate (DDR) signals that are clocked on both edges of DMD_DCLK.

All 15 DMD data signals are use to interface to the DLP3000.
DMD_D1 N14
DMD_D2 M14
DMD_D3 N15
DMD_D4 P13
DMD_D5 P14
DMD_D6 P15
DMD_D7 R15
DMD_D8 R12
DMD_D9 N11
DMD_D10 P11
DMD_D11 R11
DMD_D12 N10
DMD_D13 P10
DMD_D14 R10
DMD_DCLK N13 VCC18 O58 N/A DMD data clock (DDR)
DMD_LOADB R13 VCC18 O58 DMD_DCLK DMD data load signal (active-low). This signal requires an external pullup to VCC18.
DMD_SCTRL R14 VCC18 O58 DMD_DCLK DMD data serial control signal
DMD_TRC P12 VCC18 O58 DMD_DCLK DMD data toggle rate control
DMD_DRC_BUS L13 VCC18 O58 DMD_SAC_CLK DMD reset control bus data
DMD_DRC_STRB K13 VCC18 O58 DMD_SAC_CLK DMD reset control bus strobe
DMD_DRC_OE M13 VCC18 O58 Async DMD reset control enable (active-low). This signal requires an external pullup to VCC18.
DMD_SAC_BUS L15 VCC18 O58 DMD_SAC_CLK DMD stepped-address control bus data
DMD_SAC_CLK L14 VCC18 O58 N/A DMD stepped-address control bus clock
DMD_PWR_EN K14 VCC18 O14 Async DMD power regulator enable (active-high). This is an active-high output that should be used to control DMD VOFFSET, VBIAS, and VRESET voltages. DMD_PWR_EN is driven high as a result of the PARK input signal being set high. However, DMD_PWR_EN is held high for 500 µs after the PARK input signal is set low before it is driven low. A weak external pulldown resistor is recommended to keep this signal at a known state during power-up reset.
SDRAM INTERFACE
MEM_CLK_P D1 VCC18 O74 N/A mDDR memory, differential memory clock
MEM_CLK_N E1 VCC18 O74 N/A
MEM_A0 P1 VCC18 O64 MEM_CLK mDDR memory, multiplexed row and column address
MEM_A1 R3
MEM_A2 R1
MEM_A3 R2
MEM_A4 A1
MEM_A5 B1
MEM_A6 A2
MEM_A7 B2
MEM_A8 D2
MEM_A9 A3
MEM_A10 P2
MEM_A11 B3
MEM_A12 D3
MEM_BA0 M3 VCC18 O64 MEM_CLK mDDR memory, bank select
MEM_BA1 P3
MEM_RAS P4 VCC18 O64 MEM_CLK mDDR memory, row address strobe (active-low)
MEM_CAS R4 VCC18 O64 MEM_CLK mDDR memory, column address strobe (active-low)
MEM_WE R5 VCC18 O64 MEM_CLK mDDR memory, write enable (active-low)
MEM_CS J3 VCC18 O64 MEM_CLK mDDR memory, chip select (active-low)
MEM_CKE C1 VCC18 O64 MEM_CLK mDDR memory, clock enable (active-high)
MEM_LDQS J2 VCC18 B64 N/A mDDR memory, lower byte, R/W data strobe
MEM_LDM J1 VCC18 O64 MEM_LDQS mDDR memory, lower byte, write data mask
MEM_UDQS G1 VCC18 B64 N/A mDDR memory, upper byte, R/W data strobe
MEM_UDM H1 VCC18 O64 MEM_UDQS mDDR memory, upper byte, write data mask
MEM_DQ0 N1 VCC18 B64 MEM_LDQS mDDR memory, lower byte, bidirectional R/W data
MEM_DQ1 M2
MEM_DQ2 M1
MEM_DQ3 L3
MEM_DQ4 L2
MEM_DQ5 K2
MEM_DQ6 L1
MEM_DQ7 K1
MEM_DQ8 H2 VCC18 B64 MEM_UDQS mDDR memory, upper byte, bidirectional R/W data
MEM_DQ9 G2
MEM_DQ10 H3
MEM_DQ11 F3
MEM_DQ12 F1
MEM_DQ13 E2
MEM_DQ14 F2
MEM_DQ15 E3
LED DRIVER INTERFACE
RPWM N8 VCC18 O14 Async Red LED PWM signal used to control the LED current(6).
GPWM P9 VCC18 O14 Async Green LED PWM signal used to control the LED current(6).
BPWM R8 VCC18 O14 Async Blue LED PWM signal used to control the LED current(6).
LED_SEL_0 R6 VCC18 O14 Async

LED enable SELECT. Controlled by DMD sequence timing.
LED_SEL(1:0) Selected LED
00 None
01 Red
LED_SEL_1 N6 10 Green
11 Blue
A decode circuit is required to decode the selected LED enable.
LEDDRV_ON P7 VCC18 O14 Async LED driver master enable. Active-high output control to external LED driver logic. This signal is driven high 100 ms after LED_ENABLE is driven high. Driven low immediately when either LED_ENABLE or PARK is driven low.
LED_ENABLE A11 VCC_ INTF I3 Async LED enable (active-high input). A logic low on this signal forces LEDDRV_ON low and LED_SEL(1:0) = 00b. These signals are enabled 100 ms after LED_ENABLE transitions from low to high.
RED_EN B5 VCC18 B18 Async When not used with an optional FPGA, this signal should be connected to the RED LED enable circuit. When RED_EN is high, the red LED is enabled. When RED_EN is low, the red LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
GREEN_EN A7 When not used with an optional FPGA, this signal should be connected to the green LED enable circuit. When GREEN_EN is high, the green LED is enabled. When GREEN_EN is low, the green LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
BLUE_EN C8 When not used with an optional FPGA, this signal should be connected to the blue LED enable circuit. When BLUE_EN is high, the blue LED is enabled. When BLUE_EN is low, the blue LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
WHITE POINT CORRECTION LIGHT SENSOR I/F
CMP_OUT A6 VCC18 I1 Async Successive approximation ADC comparator output (DLPC300 input). Assumes a successive approximation ADC is implemented with a light sensor and/or thermocouple feeding one input of an external comparator and the other side of the comparator driven from the DLPC300 CMP_PWM pin. If not used, this signal should be pulled down to ground.
CMP_PWM B7 VCC18 O14 Async Successive approximation comparator pulse-duration modulation input. Supplies a PWM signal to drive the successive approximation ADC comparator used in light-to-voltage light sensor applications. Should be left unconnected if this function is not used.
CMP_PWR P5 VCC18 B14 Async Power control signal for the WPC light sensor and other analog support circuits using the DLPC300 ADC. Alternatively, it provides general-purpose I/O to the WPC microprocessor internal to the DLPC300. Should be left unconnected if not used.
TRIGGER CONTROL
OUTPUT_TRIGGER N9 VCC18 B18 Async Trigger output. Indicates that a pattern or image is displayed on the screen and is ready to be captured. With an optional FPGA, this signal is connected to the FPGA trigger input. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor.
PATTERN CONTROL
PATTERN_INVERT C7 VCC18 B18 Async Inverts the current 1-bit pattern held in the DLPC300 buffer. When used with an optional FPGA, this signal should be connected to DMC_TRC of the FPGA. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor.
OPTIONAL FPGA BUFFER MANAGEMENT INTERFACES
RD_BUF0 B6 VCC18 B18 Async When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[0] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
RD_BUF1/I2C_ADDR_SEL R9 This signal is sampled when RESET is deasserted to choose between two predefined 7-bit I2C slave addresses. If I2C_ADDR_SEL signal is pulled-low, then the DLPC300's I2C slave address is 1Bh. If I2C_ADDR_SEL signal is pulled-high, then the DLPC300's I2C slave address is 1Dh. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[1] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is set to input upon deassertion of RESET and configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
BUFFER_SWAP A8 When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to BUFF_SWAP_SEQ of the FPGA. BUFFER_SWAP indicates to the FPGA when to advance the buffer. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register.
CONTROLLER MANUFACTURER TEST SUPPORT
TEST_EN A9 VCC_INTF I3 N/A Reserved for test. Should be connected directly to ground on the PCB for normal operation. Includes weak internal pulldown
BOARD LEVEL TEST AND DEBUG
JTAGTDI P6 VCC18 I1 JTAGTCK JTAG, serial data in. Includes weak internal pullup
JTAGTCK N5 VCC18 I1 N/A JTAG, serial data clock. Includes weak internal pullup
JTAGTMS N7 VCC18 I1 JTAGTCK JTAG, test mode select. Includes weak internal pullup
JTAGTDO R7 VCC18 I14 JTAGTCK JTAG, serial data out
JTAGRST P8 VCC18 I1 ASYNC JTAG, RESET (active-low). Includes weak internal pullup. This signal must be tied to ground, through an external 15-kΩ or less resistor for normal operation.
(1) Each device connected to the SPI bus must operate from VCC_FLSH.
(2) PDATA[23:0] bus mapping is pixel-format and source-mode dependent. See later sections for details.
(3) Unused inputs should be pulled down to ground through an external resistor.
(4) VSYNC, HSYNC and data valid polarity is software programmable.
(5) Pixel clock capture edge is software programmable.
(6) All LED PWM signals are forced high when LEDDRV_ON = 0, SW LED control is disabled, or the sequence stops.

Pin Functions — Power and Ground(1)

POWER GROUP PIN NUMBERS DESCRIPTION
VDD10 D5, D9, F4, F12, J4, J12, M6, M8, M11 1-V core logic power supply (9)
VDD_PLL H12 1-V power supply for the internal PLL (1)
VCC18 C4, D8, E4, G3, K3, K12, L4, M5, M9, M12, N4, N12 1.8-V power supply for all I/O other than the host/ video interface and the SPI flash buses (12)
VCC_FLSH D6 1.8- , 2.5- or 3.3-V power supply for SPI flash bus I/O (1)
VCC_INTF D11, E12 1.8- , 2.5- or 3.3-V power supply for all I/Os on the host/video interface (includes I2C, PDATA, video syncs, PARK and LED_ENABLE pins) (2)
GND D4, D7, D10, D12, G4, G12, H4, K4, L12, M4, M7, M10 Common ground (12)
RTN_PLL J13 Analog ground return for the PLL (This should be connected to the common ground GND through a ferrite (1)
Reserved B9, C2, C3, C6, N2, N3
Reserved B10 This pin must be pulled up to VCC_INTF
(1) 132 total signal I/O pins, 38 total power/ground pins, 7 total reserved pins