ZHCSD23A October   2014  – February 2016 DLP6500FYE


  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Typical Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
      2. 7.5.2 Numerical Aperture and Stray Light Control
      3. 7.5.3 Pupil Match
      4. 7.5.4 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PCB Recommendations
    2. 10.2 Layout Example
      1. 10.2.1 Board Stack and Impedance Requirements
        1. Power Planes
        2. LVDS Signals
        3. Critical Signals
        4. Device Placement
        5. Device Orientation
        6. Fiducials
  11. 11器件文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息


请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • FYE|350
散热焊盘机械数据 (封装 | 引脚)

10 Layout

10.1 Layout Guidelines

The DLP6500FYE along with one DLPC900 controller provides a solution for many applications including structured light and video projection. This section provides layout guidelines for the DLP6500FYE.

10.1.1 General PCB Recommendations

The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches +/- 10%, using standard FR-4 material, and applies after all lamination and plating processes, measured from copper to copper.

Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity. Refer to Related Documents for the DLPC900 Digital Controller Data Sheet for related information on the DMD Interface Considerations.

High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface) is dependent on the following factors:

  • Total length of the interconnect system
  • Spacing between traces
  • Characteristic impedance
  • Etch losses
  • How well matched the lengths are across the interface

Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

  • Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
  • Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.

DLPC900 I/O timing parameters can be found in DLPC900 Digital Controller Data Sheet. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy to determine.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these recommendations may work, but should be confirmed with PCB signal integrity analysis or lab measurements.

10.2 Layout Example

10.2.1 Board Stack and Impedance Requirements

Refer to Figure 18 for guidance on the parameters.

PCB design:
Configuration: Asymmetric dual stripline
Etch thickness (T): 1.0-oz copper (1.2 mil)
Flex etch thickness (T): 0.5-oz copper (0.6 mil)
Single-ended signal impedance: 50 Ω (±10%)
Differential signal impedance: 100 Ω (±10%)
PCB stack-up:
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground.
Dielectric FR4, (Er): 4.2 (nominal)
Signal trace distance to reference plane 1 (H1): 5.0 mil (nominal)
Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal)
DLP6500FYE PCB_Stack_Geometries.gif Figure 18. PCB Stack Geometries

Table 5. General PCB Routing (Applies to All Corresponding PCB Signals)

Line width (W) Escape routing in ball field 4
PCB etch data or control 7
PCB etch clocks 7
Differential signal pair spacing (S) PCB etch data or control N/A 5.75(1)
PCB etch clocks N/A 5.75(1)
Minimum differential pair-to-pair spacing (S) PCB etch data or control N/A 20
PCB etch clocks N/A 20
Escape routing in ball field 4
Minimum line spacing to other signals (S) PCB etch data or control 10
PCB etch clocks 20
Maximum differential pair P-to-N length mismatch Total data N/A 12
Total data N/A 12
(1) Spacing may vary to maintain differential impedance requirements

Table 6. DMD Interface Specific Routing

D_AP(15:0)/ D_AN(15:0)
DCKA_P/ DCKA_N ± 150
(± 3.81)
D_BP(15:0)/ D_BN(15:0)
DCKB_P/ DCKB_N ± 150
(± 3.81)

Number of layer changes:

  • Single-ended signals: Minimize
  • Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair should not change layers.

Table 7. DMD Signal Routing Length(1)

DMD (LVDS) 50 375 mm
(1) Max signal routing length includes escape routing.

Stubs: Stubs should be avoided.

Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω internally.

Connector (DMD-LVDS interface bus only):

High-speed connectors that meet the following requirements should be used:

  • Differential crosstalk:< 5%
  • Differential impedance: 75 to 125 Ω

Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers shall have the predominant traces routed orthogonal to each other.

These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4 ps, assuming 175 ps/inch FR4 propagation delay.

These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.

Both the DLPC900 output timing parameters and the DLP6500FYE DMD input timing parameters include timing budget to account for their respective internal package routing skew. Power Planes

Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by 0.2”.

Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes should be connected together with a minimum distance between connections of 0.5”. Extra vias are not required if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and signal vias should be inside the perimeter ring of ground vias.

Power and Ground pins of each component shall be connected to the power and ground planes with one via for each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. Ground plane slots are NOT allowed.

Route VOFFSET, VBIAS, and VRESET as a wide trace >20mils (wider if space allows) with 20 mils spacing. LVDS Signals

The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation such that constant differential impedance (as in section Board Stack and Impedance Requirements ) is maintained throughout the length. Avoid sharp turns and layer switching while keeping lengths to a minimum. The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair. Critical Signals

The critical signals on the board must be hand routed in the order specified below. In case of length matching requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.

Table 8. Timing Critical Signals

1 D_AP(0:15), D_AN(0:15), DCLK_AP, DCLK_AN, SCTRL_AN, SCTRL_AP, D_BP(0:15), D_BN (0:15), DCLK_BP, DCLK_BN, SCTRL_BN, SCTRL_BP Refer to Table 5 and Table 6 Internal signal layers. Avoid layer switching when routing these signals.
2 RESET_ADDR_(0:3),
Internal signal layers. Top and bottom as required.
4 Others No matching/length requirement Any Device Placement

Unless otherwise specified, all major components should be placed on top layer. Small components such as ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are side by side as much as possible and place the smaller value capacitor closer to the device. Device Orientation

It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented with the “+” terminal the same direction and likewise for the vertically oriented ones. Fiducials

Fiducials for automatic component insertion should be placed on the board according to the following guidelines or on recommendation from manufacturer:

  • Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB.
  • Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing <0.05").
  • Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad).