ZHCSO64C September   2020  – January 2025 DLP471TE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Impedance Requirements
    3. 9.3 Layers
    4. 9.4 Trace Width, Spacing
    5. 9.5 Power
    6. 9.6 Trace Length Matching Recommendations
  11. 10Device and Documentation Support
    1. 10.1 第三方产品免责声明
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

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订购信息

5.8 Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
LVCMOS
trRise time(1)20% to 80% reference points25ns
tfFall time(1)80% to 20% reference points25ns
LOW SPEED INTERFACE (LSIF)
trRise time(2)20% to 80% reference points450ps
tfFall time(2)80% to 20% reference points450ps
tW(H)Pulse duration high(3)LS_CLK. 50% to 50% reference points3.1ns
tW(L)Pulse duration low(3)LS_CLK. 50% to 50% reference points3.1ns
tsuSetup time(4)LS_WDATA valid before rising edge of LS_CLK (differential)1.5ns
thHold time(4)LS_WDATA valid after rising edge of LS_CLK (differential)1.5ns
HIGH SPEED SERIAL INTERFACE (HSSI)
trRise time(5)(6)—datafrom -A1 to A1 minimum eye height specification50115ps
Rise time(5)(6)—clockfrom -A1 to A1 minimum eye height specification50135ps
tfFall time(5)(6)—datafrom A1 to -A1 minimum eye height specification50115ps
Fall time(5)(6)—clockfrom A1 to -A1 minimum eye height specification50135
tW(H)Pulse duration high(7)DCLK. 50% to 50% reference points0.275ns
tW(L)Pulse duration low(7)DCLK. 50% to 50% reference points0.275ns
(1) See Figure 5-9 for rise time and fall time for LVCMOS.
(2) See Figure 5-5 for rise time and fall time for LSIF.
(3) See Figure 5-4 for pulse duration high and low time for LSIF.
(4) See Figure 5-4 for setup and hold time for LSIF.
(5) See Figure 5-11 for rise time and fall time for HSSI Eye Characteristics.
(6) See Figure 5-10 for rise time and fall time for HSSI.
(7) See Figure 5-12 for pulse duration high and low for HSSI.
DLP471TE LSIF Waveform RequirementsFigure 5-3 LSIF Waveform Requirements
Equation 1. DLP471TE
Equation 2. DLP471TE
DLP471TE LSIF Timing RequirementsFigure 5-4 LSIF Timing Requirements
DLP471TE LSIF Rise, Fall Time SlewFigure 5-5 LSIF Rise, Fall Time Slew
DLP471TE LSIF Voltage RequirementsFigure 5-6 LSIF Voltage Requirements
DLP471TE LSIF Equivalent InputFigure 5-7 LSIF Equivalent Input
DLP471TE LVCMOS Input HysteresisFigure 5-8 LVCMOS Input Hysteresis
DLP471TE LVCMOS Rise, Fall Time Slew RateFigure 5-9 LVCMOS Rise, Fall Time Slew Rate
DLP471TE HSSI Waveform Requirements
A. See Equation 1 and Equation 2.
Figure 5-10 HSSI Waveform Requirements
Equation 3. DLP471TE
Equation 4. DLP471TE
DLP471TE HSSI Eye CharacteristicsFigure 5-11 HSSI Eye Characteristics
DLP471TE HSSI CLK CharacteristicsFigure 5-12 HSSI CLK Characteristics