ZHCSJA4B January   2019  – May 2022 DLP4500

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Chipset Component Usage Specification
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
    5. 8.5 Micromirror Array Temperature Calculation
      1. 8.5.1 Package Thermal Resistance
      2. 8.5.2 Case Temperature
        1. 8.5.2.1 Temperature Calculation
    6. 8.6 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.6.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.6.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.6.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.6.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC350 System Interfaces
          1. 9.2.2.1.1 Control Interface
          2. 9.2.2.1.2 Input Data Interface
        2. 9.2.2.2 DLPC350 System Output Interfaces
          1. 9.2.2.2.1 Illumination Interface
          2. 9.2.2.2.2 Trigger Interface (Sync Outputs)
        3. 9.2.2.3 DLPC350 System Support Interfaces
          1. 9.2.2.3.1 Reference Clock
          2. 9.2.2.3.2 PLL
          3. 9.2.2.3.3 Program Memory Flash Interface
        4. 9.2.2.4 DMD Interfaces
          1. 9.2.2.4.1 DLPC350 to DMD Digital Data
          2. 9.2.2.4.2 DLPC350 to DMD Control Interface
          3. 9.2.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing Requirements
    2. 10.2 DMD Power Supply Power-Up Procedure
    3. 10.3 DMD Power Supply Power-Down Procedure
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 Device Nomenclature
    2. 12.2 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6.     Trademarks
    7. 12.6 Electrostatic Discharge Caution
    8. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT
SUPPLY VOLTAGES (1)
VCC Supply voltage for LVCMOS core logic 2.375 2.5 2.625 V
VREF Supply voltage for LVCMOS DDR interface 1.6 1.9 2 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (3) (2) 8.25 8.5 8.75 V
VBIAS Supply voltage for micromirror electrode (3) 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V
|VBIAS – VOFFSET| Supply voltage delta (absolute value) (3) 8.75 V
VOLTAGE RANGE
VT+ Positive-going threshold voltage 0.4 × VREF 0.7 × VREF V
VT– Negative-going threshold voltage 0.3 × VREF 0.6 × VREF V
Vhys Hysteresis voltage (VT+ – VT–) 0.1 × VREF 0.4 × VREF V
CLOCK FREQUENCY
ƒ(CLK) DCLK clock frequency 80 120 MHz
ENVIRONMENTAL (4)
TDMD DMD temperature - operational, long-term (5) (7) 10 40 to 70 (6) °C
DMD temperature - operational, short-term –20 70 °C
TWindow DMD window temperature - operational 0 90 °C
TCERAMIC-WINDOW-DELTA DMD |ceramic TP1 - window| temperature delta - operational (8) (10) 0 15 °C
DMD long-term dewpoint (operational, non-operational) 24 °C
DMD short-term dewpoint (operational, non-operational) (9) 28 °C
ILLUMINATION
ILLUV-VIS Illumination power - spectral region <420 nm 0.68 mW/cm2
ILLVIS Illumination power - spectral region 420 to 700 nm, FQE package Thermally Limited (11) mW/cm2
Illumination power - spectral region 420 to 700 nm, FQD package Thermally Limited (11) mW/cm2
ILLIR Illumination power - spectral region >700 nm 10 mW/cm2
(1) Supply voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. All voltage values are referenced to common ground VSS.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(4) Optimal long-term performance and optical efficiency of the digital micromirror device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (storage and operating), DMD temperature, ambient humidy (storage and operating), and power on or off duty cycle.
(5) DMD temperature is the worst-case of any test point shown in Figure 8-3 or Figure 8-4, or the active array as calculated by the Micromirror Array Temperature Calculation, or any point along the window edge as defined in Figure 8-3 or Figure 8-4. The locations of thermal test point TP2 in Figure 8-3 or Figure 8-4 is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.
(6) Per Figure 7-1, the maximum operational case temperature at test points TP1 and TP2 as shown in Figure 8-3 or Figure 8-4 should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of landed duty cycle.
(7) Long-term is defined as the average over the usable life.
(8) Ceramic package and window temperature as measured at test points TP1 and TP2 in Figure 8-3 or Figure 8-4.
(9) Dew points beyond the specified long-term dew point (operating, non-operating, or storage) are for short-term conditions only, where short-term is defined as <60 cumulative days over the useful life of the device.
(10) Between any two points on or within the package including the mirror array.
(11) Refer to Micromirror Array Temperature Calculation and Temperature Calculation for information related to calculating the micromirror array temperature.
GUID-60CE3EE6-98EF-42EF-8E8E-39B857C4C4A1-low.gif Figure 7-1 Maximum Recommended DMD Temperature – Derating Curve