SLVSKK1 Data sheet | 德州仪器 TI.com.cn

SLVSKK1 December 2025 DLP3944-Q1

ADVANCE INFORMATION

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机械数据 (封装 | 引脚)

FSC|154

散热焊盘机械数据 (封装 | 引脚)

订购信息

slvskk1_oa

5.8 Timing Requirements

Over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
LVCMOS
LPSDR
t_r	Rise slew rate ⁽²⁾	(20% to 80%) × VDD⁽⁶⁾	0.25			V/ns
t_f	Fall slew rate ⁽²⁾	(80% to 20%) × VDD⁽⁶⁾	0.25			V/ns
t_r	Rise slew rate ⁽¹⁾	(30% to 80%) × VDD⁽⁶⁾	1		3	V/ns
t_f	Fall slew rate ⁽¹⁾	(70% to 20%) × VDD⁽⁶⁾	1		3	V/ns
t_W(H)	Pulse duration LS_CLK high	50% to 50% reference points⁽⁵⁾	4.2			ns
t_W(L)	Pulse duration LS_CLK low	50% to 50% reference points⁽⁵⁾	4.2			ns
t_su	Setup time	LS_WDATA valid before LS_CLK⁽⁵⁾			1.5	ns
t_h	Hold time	LS_WDATA valid after LS_CLK⁽⁵⁾			1.5	ns
SubLVDS
t_r	Rise slew rate	20% to 80% reference points⁽⁷⁾	0.7	1		V/ns
t_f	Fall slew rate	80% to 20% reference points⁽⁷⁾	0.7	1		V/ns
t_W(H)	Pulse duration DCLK high	50% to 50% reference points⁽⁸⁾	0.7			ns
t_W(L)	Pulse duration DCLK low	50% to 50% reference points⁽⁸⁾	0.7			ns
t_WINDOW	Window time ⁽¹⁾⁽³⁾	Setup time + Hold time⁽⁵⁾	0.25			ns
t_su	Setup time	HS_DATA valid before HS_CLK⁽⁸⁾			0.17	ns
t_h	Hold time	HS_DATA valid after HS_CLK⁽⁸⁾			0.17	ns
t_POWER	Power-up receiver⁽⁴⁾				200	ns

(1) The specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 5-3.

(2) The specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise and fall slew rate in Figure 5-3.

(3) Window time derating example: 0.5V/ns slew rate increases the window time by 0.7ns, from 3ns to 3.7ns. See Figure 5-5.

(4) The specification is for the SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(5) See Figure 5-2.

(6) See Figure 5-3.

(7) See Figure 5-4.

(8) See Figure 5-6.