ZHCSJ26D november   2018  – july 2023 DLP3310

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-47BD6CB7-BBE8-4256-A65E-D6DBDB168B5B-low.gif Figure 5-1 FQM Package92-Pin CLGABottom View
Table 5-1 Pin Functions – Connector Pins
PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_AN(0) C6 I SubLVDS Double Data, negative 2.83
D_AN(1) D7 I SubLVDS Double Data, negative 4.00
D_AN(2) D5 I SubLVDS Double Data, negative 1.97
D_AN(3) F7 I SubLVDS Double Data, negative 4.03
D_AN(4) F5 I SubLVDS Double Data, negative 1.90
D_AN(5) G6 I SubLVDS Double Data, negative 3.08
D_AN(6) H5 I SubLVDS Double Data, negative 2.23
D_AN(7) H7 I SubLVDS Double Data, negative 3.88
D_AP(0) C5 I SubLVDS Double Data, positive 2.72
D_AP(1) D6 I SubLVDS Double Data, positive 3.89
D_AP(2) D4 I SubLVDS Double Data, positive 1.87
D_AP(3) F6 I SubLVDS Double Data, positive 3.93
D_AP(4) F4 I SubLVDS Double Data, positive 1.79
D_AP(5) G5 I SubLVDS Double Data, positive 2.97
D_AP(6) H4 I SubLVDS Double Data, positive 2.12
D_AP(7) H6 I SubLVDS Double Data, positive 3.78
D_BN(0) C20 I SubLVDS Double Data, negative 2.23
D_BN(1) D19 I SubLVDS Double Data, negative 3.27
D_BN(2) D21 I SubLVDS Double Data, negative 1.27
D_BN(3) F19 I SubLVDS Double Data, negative 3.52
D_BN(4) F21 I SubLVDS Double Data, negative 1.34
D_BN(5) G20 I SubLVDS Double Data, negative 2.55
D_BN(6) H21 I SubLVDS Double Data, negative 1.71
D_BN(7) H19 I SubLVDS Double Data, negative 3.37
D_BP(0) C21 I SubLVDS Double Data, positive 2.13
D_BP(1) D20 I SubLVDS Double Data, positive 3.16
D_BP(2) D22 I SubLVDS Double Data, positive 1.17
D_BP(3) F20 I SubLVDS Double Data, positive 3.42
D_BP(4) F22 I SubLVDS Double Data, positive 1.23
D_BP(5) G21 I SubLVDS Double Data, positive 2.44
D_BP(6) H22 I SubLVDS Double Data, positive 1.61
D_BP(7) H20 I SubLVDS Double Data, positive 3.27
DCLK_AN E6 I SubLVDS Double Clock, negative 2.56
DCLK_AP E5 I SubLVDS Double Clock, positive 2.46
DCLK_BN E20 I SubLVDS Double Clock, negative 2.05
DCLK_BP E21 I SubLVDS Double Clock, positive 1.95
CONTROL INPUTS
LS_WDATA B3 I LPSDR(1) Single Write data for low speed interface 1.78
LS_CLK B5 I LPSDR Single Clock for low-speed interface 1.78
DMD_DEN_ARSTZ B2 I LPSDR Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 0.85
LS_RDATA_A B7 O LPSDR Single Read data for low-speed interface 4.19
LS_RDATA_B B4 O LPSDR Single Read data for low-speed interface 2.18
POWER
VBIAS(3) A6 Power Supply voltage for positive bias level at micromirrors
VBIAS(3) A22 Power
VOFFSET(3) B21 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors
VOFFSET(3) G2 Power
VRESET A5 Power Supply voltage for negative reset level at micromirrors
VRESET A23 Power
VDD(3) C2 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes
VDD A19 Power
VDD A20 Power
VDD A21 Power
VDD B20 Power
VDD D2 Power
VDD D3 Power
VDD D23 Power
VDD E2 Power
VDD F2 Power
VDD F3 Power
VDD F23 Power
VDDI B6 Power Supply voltage for SubLVDS receivers
VDDI B19 Power
VDDI C3 Power
VDDI C23 Power
VDDI E3 Power
VDDI E23 Power
VDDI G3 Power
VDDI G23 Power
VSS A2 Ground Common return
Ground for all power
VSS A3 Ground
VSS A4 Ground
VSS A7 Ground
VSS A24 Ground
VSS B22 Ground
VSS B23 Ground
VSS B24 Ground
VSS C4 Ground
VSS C7 Ground
VSS C19 Ground
VSS C22 Ground
VSS E4 Ground
VSS E7 Ground
VSS E19 Ground
VSS E22 Ground
VSS G4 Ground
VSS G7 Ground
VSS G19 Ground
VSS G22 Ground
VSS G24 Ground
VSS H2 Ground
VSS H3 Ground
VSS H23 Ground
VSS H24 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQM ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 5-2 Pin Functions – Test Pads
NUMBER SYSTEM BOARD
A1 Do not connect.
A17 Do not connect.
A18 Do not connect.
B8 Do not connect.
B17 Do not connect.
B18 Do not connect.
C8 Do not connect.