ZHCSMH3B February   2022  – December 2023 DLP2021-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 说明（续）
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14.     21
    15. 6.10 Micromirror Array Optical Characteristics
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 Device Handling
    8. 11.8 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

Figure 5-1 FQU Package64-Pin LGABottom View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DATA(0) A2 LVCMOS input Data bus. Synchronous to rising edge and falling edge of DCLK
DATA(1) A4
DATA(2) B2
DATA(3) B3
DATA(4) B5
DATA(5) C2
DATA(6) C3
DATA(7) B4
DATA(8) C5
DATA(9) D2
DCLK F4 Data clock
LOADB F3 Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK
SCTRL E4 Serial control (sync). Synchronous to rising edge and falling edge of DCLK
TRC F2 Toggle rate control. Synchronous to rising edge and falling edge of DCLK
DAD_BUS B15 Reset control serial bus. Synchronous to rising edge of SAC_CLK
RESET_OEZ C15 Active low. Output enable signal for internal reset driver circuitry
RESET_STROBE B13 Rising edge on RESET_STROBE latches in the control signals
SAC_BUS A15 Stepped address control serial bus. Synchronous to rising edge of SAC_CLK
SAC_CLK A14 Stepped address control clock
TEMP_MINUS G13 Analog input Calibrated temperature diode used to assist accurate temperature measurements of DMD die
TEMP_PLUS G2
VBIAS D15 Power Power supply for positive bias level of mirror reset signal
VCC A5, B12, C14, D12, F13, G3 Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down
VOFFSET E14 Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal
VRESET D14 Power supply for negative reset level of mirror reset signal
VSS A3, A13, B14, C4, C12, C13, D13, E3, E5, E12, F12, F14, G4, G12 Common return for all power
RESERVED A1, A12, A16,B1, B16, D3, D4, D5, E2, E13,E15, F1, F5, F15, F16, G1, G5, G14, G15, G16 Reserved Do not connect.