ZHCSKH5C May 2008 – November 2019 DAC9881
PRODUCTION DATA.
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several DACs, the SDO pin may be used to daisy-chain several devices together.
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the SDI input on the next DAC in the chain, a multi-DAC interface is constructed. 24 clock pulses are required for each DAC in the chain. Therefore, the total number of clock cycles must be equal to (24 x N), where N is the total number of devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action prevents any further data from being clocked into the input shift register. The contents in the shift registers are transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers, and all analog outputs update simultaneously.