ZHCSHP3 February 2018 DAC8771
PRODUCTION DATA.
The SPI Shift Register is 24 bits wide (refer to the Frame Error Checking section for 32-bit frame mode). The default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 1.
BIT 23:BIT 16 | BIT 15:BIT 0 |
---|---|
Address byte | Data word |