The DAC80004, DAC70004, and DAC60004 are quad-channel, 16-bit, voltage-output DACs with internal reference buffers and output buffers. Each channel consists of an R-2R ladder configuration with the 4 MSBs segmented, followed by an operational amplifier, as shown in Figure 51. The DACx0004 devices have a constant impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders. With the production trim process these devices have excellent dc accuracy and ac performance.
The input coding to the DACx0004 is straight binary, so the ideal output voltage is given by Equation 1:
N = resolution in bits; either 16 (DAC80004), 14 (DAC70004) or 12 (DAC60004)
DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2N –1
REFIN = DAC reference voltage
The DACx0004 output buffer amplifier is capable of generating near rail-to-rail voltages on its output, giving a maximum output range of 0 V to REFIN. It is capable of driving a load of 5 kΩ in parallel with 2 nF to GND. The typical slew rate of this amplifier while driving no load is 1.5 V/µs, with a full-scale settling time of 8 µs to 1 LSB of the final value as shown in Figure 43 and Figure 44. The current consumption of the amplifier (unloaded) is 1 mA/channel (typical). The DACx0004 output amplifier also implements a short circuit current limiting circuit. The default value of short circuit limit is 40 mA, however this can be reduced to 30 mA using dedicated bits (1 per channel) via SPI command 1010 (see Table 2).
The DACx0004 requires an external reference to operate. The reference input pin has the following input range:
2.2 V to (VDD – 0.2) for 2.7 V ≤ VDD ≤ 4.5 V
2.2 V to VDD for 4.5 V ≤ VDD ≤ 5.5 V
The DACx0004 contains a dedicated reference buffer for each DAC channel. The REFIN pin drives the input of these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin. This simplifies the external reference drive circuit for the device.
The DACx0004 contain a power-on-reset circuit that controls the output voltage during power up. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1).
The DAC power-on reset code for all of the channels depends on the state of the POR pin at power up (see Pin Configuration and Functions).
Each DAC channel remains that way until a valid load command is written to it. All device registers are reset at power up as shown in Table 1.
|REGISTER NAME||DACx0004 - POWER-ON RESET VALUE|
|DAC latches (per channel)||If POR pin = '0' then Zero Scale else Mid scale|
|DAC buffers (per channel)||If POR pin= '0' then Zero Scale else Mid scale|
|Power down (per channel)||00 – Normal mode|
|Clear mode||00 – Clear to Zero|
|Ignore LDAC (per channel)||0000 – Do not ignore|
|Daisy chain||0 – Daisy chain disabled, DAC update at 32nd SCLK falling edge|
|Short circuit limit (per channel)||0000 – all DACs 40 mA|
When the device powers up, an IPOR circuit sets the device in default mode as shown in Table 1. The IPOR circuit requires specific VDD levels, as indicated in Figure 52, to ensure discharging of internal capacitors and to reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms. When VDD drops below 2.4 V but remains above 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power supply conditions. In this case, In this case a power-down reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur.
The DACx0004 devices have a 4-wire serial interface: SYNC, SCLK, SDIN, and SDO (see Pin Configuration and Functions). The serial interface (3-wire and 4-wire) is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs and it operates up to 50 MHz. See the Write Mode Stand-Alone Timing and Write Mode Daisy-Chain Timing diagrams (see Figure 1 and Figure 2) for examples of typical write and read sequences. The input shift register is 32 bits wide.
The serial clock SCLK can be a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin (TSSOP-14 and VSON-14 packages) is in a Hi-Z state. The device internal registers are updated from the shift register on the 32nd falling edge of SCLK.
For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC register updates on the 32nd SCLK falling edge. However, if SYNC is brought high before the 32nd SCLK falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 53).
The READ command is used to start read-back operation. However, before read-back operation can be initiated, the SDO pin must be enabled by setting the DSDO bit to '1'; this bit is disabled by default. Read-back operation is then started by executing a READ command (R/W bit = '1', see Table 3). Bits C3 to C0 select the register to be read. The remaining data in the command are don’t care bits. During the next SPI operation, the data appearing on the SDO output are from the previously addressed register. For a read of a single register, a NOP (No Operation) command (1110) can be used to clock out the data from the selected register on SDO. Multiple registers can be read if multiple READ commands are issued (see Figure 54).
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together (see Figure 55). Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial interface lines. The daisy-chain feature can be enabled by writing a logic '1' to the DSDO bit (see Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0.
The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI shift register when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appear on the SDO line. The data bits are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed (see Figure 2). Each device in the system requires 32 clock pulses. Therefore, the total number of clock cycles must equal 32 × N, where N is the total number of DACx0004s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI shift registers to the device internal registers for each device in the daisy-chain and prevents any further data from being clocked in. The serial clock can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the data.
For daisy-chain operation, the SYNC line stays low for at least 32 × N SCLK cycles, where N is the number of DACx0004s in the daisy chain. If SYNC is brought high before a multiple 32 SCLKs, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56).
The SPI shift register is 32 bits wide, as shown in Table 2. The shift register command mapping is shown in Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from MSB (D19) to LSB (D4 - 16 bits, D6 - 14 bits, D8 - 12 bits).
|Don't Cares||R/W||Command Bits||Channel Address Bits||16/14/12-Bit DAC Data left alligned/Power Down Bits/Device Ready bit||Mode Bits|
|D31 - D28||D27 - D24||D23 - D20||D19 - D16||D15 - D12||D11 - D08||D07 - D04||D03 - D00||Commands|
|X||W/R||0||0||0||0||Channel Address||DAC Data||DAC Data||DAC Data||DAC Data||X||Write to buffer n|
|X||W||0||0||0||1||Channel Address||X||X||X||X||X||Update DAC n|
|X||W||0||0||1||0||Channel Address||DAC Data||DAC Data||DAC Data||DAC Data||X||Write to buffer n and update all DACs (Software LDAC)|
|X||W||0||0||1||1||Channel Address||DAC Data||DAC Data||DAC Data||DAC Data||X||Write to buffer and update DAC n|
|X||W/R||0||1||0||0||X||X||X||X||PD1||PD0||Ch-D||Ch-C||Ch-B||Ch-A||Power up/down DAC n|
|X||W/R||0||1||0||1||X||X||X||X||X||X||X||CM1||CM0||Clear mode register|
|X||W/R||1||0||0||0||X||X||X||X||X||X||DSD0||X||Disable SDO register|
|X||W/R||1||0||1||0||X||X||X||X||X||Ch-D||Ch-C||Ch-B||Ch-A||Short circuit limit register|
|X||W||1||1||1||0||X||X||X||X||X||X||No operation (NOP)|
|CHANNEL ADDRESS BITS||DESCRIPTION|
|0||0||0||0||Select channel A|
|0||0||0||1||Select channel B|
|0||0||1||0||Select channel C|
|0||0||1||1||Select channel D|
|1||1||1||1||Select all channel|
The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24 and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09), PD0 (D08).
|POWER DOWN BITS||DESCRIPTION|
|0||0||Normal operation/power up selected channel(s) (Default)|
|0||1||Power down selected channel(s) 1 kΩ-GND|
|1||0||Power down selected channel(s) 100 kΩ-GND|
|1||1||Power down selected channel(s) Hi-Z|
It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value.
The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC power-down circuitry is shown in Figure 57.
The CLR pin is an asynchronous input pin to the DAC. When activated, this falling edge sensitive pin clears the DAC buffers and the DAC latches to zero, mid, full or user programmed code depending on the clear mode register (see Table 6). The default setting for clear operation is clear to 0 V. The device exits clear mode on the 32nd falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and changes the input and DAC registers immediately. Additionally, all DAC registers can also be cleared via SPI command 1011. Note that the clear mode bits determine the clear code for all the DACs upon clear operation.
The DACx0004 implement four different clear modes. These modes are accessed by setting command bits D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3). Based on the value of clear mode register (see Table 6), all of the DAC and the buffers are cleared to zero, mid, or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued.
The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24.
|CLEAR MODE BITS||DESCRIPTION|
|0||0||All DACs clear to zero scale (default)|
|0||1||All DACs clear to mid scale|
|1||0||All DACs clear to full scale|
The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode.
In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then pulse the LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is pulsed low.
In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.
Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word (D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin.
See Table 7 for more information.
|LDAC REGISTER BITS (D03 – D00)||DAC UPDATE|
|0||Determined by LDAC pin (Default)|
|1||DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels see LDAC as 0|
The DACx0004 output amplifier has a default short circuit limit of 40 mA. However, this limit can be reduced to 30 mA by using command 1010 on bits D28 – D24 and selecting channel(s) (D03 – D00). Please note that DACx0004 has a dedicated bit per channel, this allows the user to set different short circuit limit for different DAC output channels.
|SHORT CIRCUIT LIMIT REGISTER BITS (D03 – D00)||DAC SHORT CIRCUIT LIMIT|
|0||DAC output short circuit limit = 40 mA (Default)|
|1||DAC output short circuit limit = 30 mA|
The DACx0004 implements a read-only status register (see Table 3). This register can be read by using command 1101 on bits D28 – D24, followed by a NOP command.
Logic ‘1’ on bit D04 indicates that the device is ready to be used. This feature is useful to check if the device is ready to accept commands after power up.