ZHCSJ19E november   2018  – august 2023 DAC60501 , DAC70501 , DAC80501

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SPI Mode
    7. 7.7  Timing Requirements: I2C Standard Mode
    8. 7.8  Timing Requirements: I2C Fast Mode
    9. 7.9  Timing Requirements: I2C Fast-Mode Plus
    10. 7.10 Timing Diagrams
    11. 7.11 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 Output Amplifier
      2. 8.3.2 Internal Reference
        1. 8.3.2.1 Solder Heat Reflow
      3. 8.3.3 Power-On-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 SPI Mode
          1. 8.5.1.1.1 SYNC Interrupt
        2. 8.5.1.2 I2C Mode
          1. 8.5.1.2.1 F/S Mode Protocol
          2. 8.5.1.2.2 I2C Update Sequence
            1. 8.5.1.2.2.1 Address Byte
            2. 8.5.1.2.2.2 Command Byte
            3. 8.5.1.2.2.3 Data Byte (MSDB and LSDB)
          3. 8.5.1.2.3 I2C Read Sequence
    6. 8.6 Register Map
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Charge Injection
        2. 9.2.2.2 Voltage Droop
        3. 9.2.2.3 Output Offset Error
        4. 9.2.2.4 Switch Selection
        5. 9.2.2.5 Amplifier Selection
        6. 9.2.2.6 Hold Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Typical Characteristics

at TA = 25°C, VDD = 5.5 V, Internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, and DAC outputs unloaded (unless otherwise noted)

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Figure 7-3 Integral Linearity Error vs Digital Input Code
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Figure 7-5 Total Unadjusted Error vs Digital Input Code
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Figure 7-7 Differential Linearity Error vs Temperature
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Figure 7-9 Zero Code Error vs Temperature
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Figure 7-11 Full Scale Error vs Temperature
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-13 Integral Linearity Error vs Supply Voltage
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Figure 7-15 Total Unadjusted Error vs Supply Voltage
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Figure 7-17 Offset Error vs Supply Voltage
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Figure 7-19 Full Scale Error vs Supply Voltage
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Figure 7-21 Differential Linearity Error vs Reference Voltage
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Figure 7-23 Zero Code Error vs Reference Voltage
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Figure 7-25 Gain Error vs Reference Voltage
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Figure 7-27 Supply Current vs Digital Input Code
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DAC code at midscale
Figure 7-29 Supply Current vs Supply Voltage
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External reference = 2.5 V, REF-DIV = 1 and BUFF-GAIN = 0
Figure 7-31 Power Down Current vs Supply Voltage
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-33 Source and Sink Capability
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REF-DIV = 1 and BUFF-GAIN = 0
 
Figure 7-35 Source and Sink Capability
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DAC code transition from midscale to midscale – 1 LSB,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-37 Glitch Impulse, Falling Edge, 1‑LSB Step
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-39 Full-Scale Settling Time, Falling Edge
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REF-DIV = 0 and BUFF-GAIN = 0
 
Figure 7-41 Power-off Glitch
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fo = 1 kHz, fs = 400 kHz, includes 7 harmonics,
measurement bandwidth = 20 kHz, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-43 DAC Output THD+N vs Frequency
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DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-45 DAC Output Noise 0.1 Hz to 10 Hz
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DAC code at midscale, external reference = 2.5 V,
SCLK = 1 MHz, REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-47 Clock Feedthrough
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Figure 7-49 Internal Reference Voltage vs Supply Voltage
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Figure 7-51 Internal Reference Noise Density vs Frequency
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Figure 7-53 Internal Reference Temperature Drift Histogram
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Figure 7-55 Internal Reference Temperature Drift (Pre- and Post-Solder) Histogram
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Figure 7-4 Differential Linearity Error vs Digital Input Code
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Figure 7-6 Integral Linearity Error vs Temperature
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Figure 7-8 Total Unadjusted Error vs Temperature
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Figure 7-10 Offset Error vs Temperature
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Figure 7-12 Gain Error vs Temperature
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-14 Differential Linearity Error vs Supply Voltage
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Figure 7-16 Zero Code Error vs Supply Voltage
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Figure 7-18 Gain Error vs Supply Voltage
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Figure 7-20 Integral Linearity Error vs Reference Voltage
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Figure 7-22 Total Unadjusted Error vs Reference Voltage
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Figure 7-24 Offset Error vs Reference Voltage
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Figure 7-26 Full Scale Error vs Reference Voltage
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DAC code at midscale
Figure 7-28 Supply Current vs Temperature
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-30 Power Down Current vs Temperature
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External reference = 2.5 V
Figure 7-32 Headroom and Footroom vs Load Current
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REF-DIV = 0 and BUFF-GAIN = 1
Figure 7-34 Source and Sink Capability
GUID-871DEF9B-F252-4BAE-9358-107AC600051B-low.gif
DAC code transition from midscale – 1 to midscale LSB,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-36 Glitch Impulse, Rising Edge, 1‑LSB Step
GUID-05DA302C-777A-431E-A1C7-63793FD366EC-low.gif
REF-DIV = 0 and BUFF-GAIN = 0
 
Figure 7-38 Full-Scale Settling Time, Rising Edge
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REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-40 Power-on Glitch
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DAC code at midscale, VDD = 5.0 V + 0.2 VPP,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-42 DAC Output AC PSRR vs Frequency
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Gain = 1X (REF-DIV = 1 and BUFF-GAIN = 1),
external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-44 DAC Output Noise Spectral Density
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DAC code at midscale, internal reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 7-46 DAC Output Noise 0.1 Hz to 10 Hz
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30 units
 
Figure 7-48 Internal Reference Voltage vs Temperature
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Figure 7-50 Internal Reference Voltage vs Time
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Figure 7-52 Internal Reference Noise, 0.1 Hz to 10 Hz
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Figure 7-54 Internal Reference Initial Accuracy (Pre- and Post-Solder) Histogram