SNAS424D August   2007  – April 2016 DAC088S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Architecture
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Daisy Chain Operation
      3. 8.5.3 Serial Input Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Examples Programming the DAC088S085
        1. 9.1.1.1 Updating DAC Outputs Simultaneously
        2. 9.1.1.2 Updating DAC Outputs Independently
      2. 9.1.2 Bipolar Operation
      3. 9.1.3 Variable Current Source Output
      4. 9.1.4 DSP and Microprocessor Interfacing
        1. 9.1.4.1 ADSP-2101 and ADSP2103 Interfacing
        2. 9.1.4.2 80C51 and 80L51 Interface
        3. 9.1.4.3 68HC11 Interface
        4. 9.1.4.4 Microwire Interface
      5. 9.1.5 Industrial Application
    2. 9.2 Typical Applications
      1. 9.2.1 ADC Reference
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Attenuator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Specification Definitions
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6 Pin Configuration and Functions

RGH Package
16-Pin WQFN
Top View
PW Package
16-Pin TSSOP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
WQFN TSSOP
DIN 15 1 Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
DOUT 16 2 Digital Output Serial Data Output. DOUT is used in daisy chain operation and is connected directly to a DIN pin on another DAC088S085. Data is not available at DOUT unless SYNC remains low for more than 16 SCLK cycles.
GND 8 10 Ground Ground reference for all on-chip circuitry.
SCLK 14 16 Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
SYNC 13 15 Digital Input Frame Synchronization Input. When this pin goes low, data is written into the DAC's input shift register on the falling edges of SCLK. After the 16th falling edge of SCLK, a rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
VA 5 7 Supply Power supply input. Must be decoupled to GND.
VOUTA 1 3 Analog Output Channel A Analog Output Voltage.
VOUTB 2 4 Analog Output Channel B Analog Output Voltage.
VOUTC 3 5 Analog Output Channel C Analog Output Voltage.
VOUTD 4 6 Analog Output Channel D Analog Output Voltage.
VOUTE 12 14 Analog Output Channel E Analog Output Voltage.
VOUTF 11 13 Analog Output Channel F Analog Output Voltage.
VOUTG 10 12 Analog Output Channel G Analog Output Voltage.
VOUTH 9 11 Analog Output Channel H Analog Output Voltage.
VREF1 6 8 Analog Input Unbuffered reference voltage shared by Channels A, B, C, and D. Must be decoupled to GND.
VREF2 7 9 Analog Input Unbuffered reference voltage shared by Channels E, F, G, and H. Must be decoupled to GND.
PAD(1) — — Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
(1) WQFN only