SGLS390G July   2009  – November 2015 CDCM7005-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic/Manual Reference Clock Switching
      2. 9.3.2 PLL Lock for Analog and Digital Detect
        1. 9.3.2.1 PLL Lock/Out-of-Lock Definition
        2. 9.3.2.2 Digital vs Analog Lock
      3. 9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs
      4. 9.3.4 Frequency Hold-Over Mode
      5. 9.3.5 Charge Pump Preset to VCC_CP / 2
      6. 9.3.6 Charge Pump Current Direction
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SPI Control Interface
      2. 9.5.2 Functional Description of the Logic
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Generation for Interpolating DACs With the CDCM7005-SP
        1. 10.1.1.1 AC-Coupled Interface to ADC/DAC
      2. 10.1.2 Phase Noise Performance
        1. 10.1.2.1 In-Band Noise Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • HFG|52
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

CDCM7005-SP has a simple power scheme. Two power supplies are needed general VCC and analog AVCC. Both supplies should have the same voltage, with individual beads to isolate them. No special power sequencing is needed. A separate supply VCC_CP is used for the charge pump. This supply should match the VCO/VCXO supply but not to exceed the maximum recommended operating voltage of AVCC/VCC.

As PD pin is active low, TI recommends to ramp up the PD with the same time as VCC and AVCC or later. The ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC.