SCAS880F August   2009  – September 2015 CDCLVP1204

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Terminal Characteristics
    6. 6.6  Electrical Characteristics: LVCMOS Input
    7. 6.7  Electrical Characteristics: Differential Input
    8. 6.8  Electrical Characteristics: LVPECL Output
    9. 6.9  Electrical Characteristics: LVPECL Output
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Test Configurations
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range(2) –0.5 4.6 V
VIN Input voltage range(3) –0.5 VCC + 0.5 V
VOUT Output voltage range(3) –0.5 VCC + 0.5 V
IIN Input current 20 mA
IOUT Output current 50 mA
TA Specified free-air temperature range (no airflow) –40 85 °C
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability..
(2) All supply voltages must be supplied simultaneously.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VCC Supply voltage 2.375 2.50/3.30 3.60 V
TA Ambient temperature –40 85 °C
TPCB PCB temperature (measured at thermal pad) 105 °C

6.4 Thermal Information

THERMAL METRIC(1)(3)(4) CDCLVP1204 UNIT
RGT (QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 51.8, 0 LFM(2) °C/W
22.6, 150 LFM(2)
19.2, 400 LFM(2)
RθJC(top) Junction-to-case (top) thermal resistance 79 °C/W
RθJP(5) Junction-to-pad thermal resistance 6.12(2) °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 19 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.12 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) 2 x 2 vias on Pad
(3) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
(4) Connected to GND with four thermal vias (0.3-mm diameter).
(5) RθJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package.

6.5 Terminal Characteristics

PARAMETER MIN TYP MAX UNIT
RPULLDOWN Input pulldown resistor 150

6.6 Electrical Characteristics: LVCMOS Input

At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Input frequency 200 MHz
Vth Input threshold voltage External threshold voltage applied to complementary input 1.1 1.8 V
VIH Input high voltage Vth + 0.1 VCC V
VIL Input low voltage 0 Vth – 0.1 V
IIH Input high current VCC = 3.6 V, VIH = 3.6 V 40 μA
IIL Input low current VCC = 3.6 V, VIL = 0 V –40 μA
ΔVT Input edge rate 20% to 80% 1.5 V/ns
ICAP Input capacitance 5 pF
(1) Figure 6 and Figure 7 show DC test setup.

6.7 Electrical Characteristics: Differential Input

At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted). (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Input frequency Clock input 2000 MHz
VIN, DIFF, PP Differential input peak-peak voltage fIN ≤ 1.5 GHz 0.1 1.5 V
1.5 GHz ≤ fIN ≤ 2 GHz 0.2 1.5 V
VICM Input common-mode level 1 VCC – 0.3 V
IIH Input high current VCC = 3.6 V, VIH = 3.6 V 40 μA
IIL Input low current VCC = 3.6 V, VIL = 0 V –40 μA
ΔV/ΔT Input edge rate 20% to 80% 1.5 V/ns
ICAP Input capacitance 5 pF
(1) Figure 5 and Figure 8 show DC test setup. Figure 9 shows AC test setup.

6.8 Electrical Characteristics: LVPECL Output

VCC = 2.375 V to 2.625 V; TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage TA ≤ 85ºC VCC – 1.26 VCC – 0.9 V
TPCB ≤ 105ºC VCC – 1.26 VCC – 0.83 V
VOL Output low voltage TA ≤ 85ºC VCC – 1.7 VCC – 1.3 V
TPCB ≤ 105ºC VCC – 1.7 VCC – 1.25 V
VOUT, DIFF, PP Differential output peak-peak voltage fIN ≤ 2 GHz 0.5 1.35 V
fIN = 125 MHz, 312.5 MHz 1.15
VAC_REF Input bias voltage(2) IAC_REF = 2 mA VCC – 1.6 VCC – 1.1 V
tPD Propagation delay VIN, DIFF, PP = 0.1 V 450 ps
VIN, DIFF, PP = 0.3 V 450 ps
tSK,PP Part-to-part skew 100 ps
tSK,O Output skew 15 ps
tSK,P Pulse skew (with 50% duty cycle input) Crossing-point-to-crossing-point distortion,
fOUT = 100 MHz
–50 50 ps
tRJIT Random additive jitter
(with 50% duty cycle input)
fOUT = 100 MHz, VIN,SE = VCC,
Vth = 1.25 V,
10 kHz to 20 MHz
0.081 ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.091 ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.041 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
0.088 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.081 ps, RMS
fOUT = 122.88 MHz,(6)(3)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.057 0.088 ps, RMS
fOUT = 122.88 MHz,(6)(3)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.057 0.088 ps, RMS
fOUT = 122.88 MHz,(6)(3)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.086 0.121 ps, RMS
fOUT = 156.25 MHz,(6)(4)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.048 0.071 ps, RMS
fOUT = 156.25 MHz,(6)(4)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.048 0.071 ps, RMS
fOUT = 156.25 MHz,(6)(4)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.068 0.097 ps, RMS
fOUT = 312.5 MHz,(6)(5)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.030 0.048 ps, RMS
fOUT = 312.5 MHz,(6)(5)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.030 0.048 ps, RMS
fOUT = 312.5 MHz,(6)(5)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.045 0.068 ps, RMS
tR/tF Output rise/fall time 20% to 80% 200 ps
IEE Supply internal current Outputs unterminated
TA ≤ 85ºC
45 mA
Outputs unterminated,
TPCB ≤ 105ºC
47 mA
ICC Output and internal supply current All outputs terminated, 50 Ω to VCC – 2
TA ≤ 85ºC
170 mA
All outputs terminated,
50 Ω to VCC – 2
TPCB ≤ 105ºC
186 mA
(1) Figure 10 and Figure 11 show DC and AC test setup.
(2) Internally generated bias voltage (VAC_REF) is for 3.3 V operation only. It is recommended to apply externally generated bias voltage for VCC < 3 V.
(3) Input source: 122.88 MHz Rohde & Schwarz SMA100A Signal Generator.
(4) Input source: 156.25 MHz Rohde & Schwarz SMA100A Signal Generator.
(5) Input source: 312.5 MHz Rohde & Schwarz SMA100A Signal Generator.
(6) Input source RMS Jitter (tRJIT_IN) and Total RMS Jitter (tRJIT_OUT) measured using Agilent E5052 Phase Noise Analyzer. Buffer device random additive jitter computed as: tRJIT = SQRT[(tRJIT_OUT)2 - (tRJIT_IN)2].

6.9 Electrical Characteristics: LVPECL Output

VCC = 3 V to 3.6 V; TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage TA ≤ 85ºC VCC – 1.26 VCC – 0.9 V
TPCB ≤ 105ºC VCC – 1.26 VCC – 0.85 V
VOL Output low voltage TA ≤ 85ºC VCC – 1.7 VCC – 1.3 V
TPCB ≤ 105ºC VCC – 1.7 VCC – 1.3 V
VOUT, DIFF, PP Differential output peak-peak voltage fIN ≤ 2 GHz 0.65 1.35 V
VAC_REF Input bias voltage IAC_REF = 2 mA VCC – 1.6 VCC – 1.1 V
tPD Propagation delay VIN, DIFF, PP = 0.1 V 450 ps
VIN, DIFF, PP = 0.3 V 450 ps
tSK,PP Part-to-part skew 100 ps
tSK,O Output skew 15 ps
tSK,P Pulse skew (with 50% duty cycle input) Crossing-point-to-crossing-point distortion,
fOUT = 100 MHz
–50 50 ps
tRJIT Random additive jitter (with 50% duty cycle input)
fOUT = 100 MHz(6)
fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.65 V,
10 kHz to 20 MHz
0.079 ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.097 ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.058 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
0.094 ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.088 ps, RMS
fOUT = 100 MHz, Input AC coupled,
VICM = VAC_REF, 12 kHz to 20 MHz
0.068 ps, RMS
Random additive jitter (with 50% duty cycle input)
fOUT = 122.88 MHz(6)
fOUT = 122.88 MHz,(2)(5)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.057 ps, RMS
fOUT = 122.88 MHz,(2)(5)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.057 ps, RMS
fOUT= 122.88 MHz,(2)(5)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.086 ps, RMS
tRJIT Random additive jitter (with 50% duty cycle input)
fOUT = 156.25 MHz(6)
fOUT = 156.25 MHz,(5)(3)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.048 ps, RMS
fOUT = 156.25 MHz,(5)(3)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.048 ps, RMS
fOUT = 156.25 MHz,(5)(3)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.068 ps, RMS
Random additive jitter (with 50% duty cycle input)
fOUT = 312.5 MHz(6)
fOUT = 312.5 MHz,(5)(4)
Square Wave, VIN-PP = 1 V,
12 kHz to 20 MHz
0.030 ps, RMS
fOUT = 312.5 MHz,(5)(4)
Square Wave, VIN-PP = 1 V,
10 kHz to 20 MHz
0.030 ps, RMS
fOUT = 312.5 MHz,(5)(4)
Square Wave, VIN-PP = 1 V,
1 kHz to 40 MHz
0.045 ps, RMS
tR/tF Output rise/fall time 20% to 80% 200 ps
IEE Supply internal current Outputs unterminated
TA ≤ 85ºC
45 mA
Outputs unterminated,
TPCB ≤ 105ºC
47 mA
ICC Output and internal supply current All outputs terminated,
50 Ω to VCC – 2
TA ≤ 85ºC
170 mA
All outputs terminated,
50 Ω to VCC – 2
TPCB ≤ 105ºC
186 mA
(1) Figure 10 and Figure 11 show DC and AC test setup.
(2) Input source: 122.88 MHz Rohde & Schwarz SMA100A Signal Generator.
(3) Input source: 156.25 MHz Rohde & Schwarz SMA100A Signal Generator.
(4) Input source: 312.5 MHz Rohde & Schwarz SMA100A Signal Generator.
(5) Input source RMS Jitter (tRJIT_IN) and Total RMS Jitter (tRJIT_OUT) measured using Agilent E5052 Phase Noise Analyzer. Buffer device random additive jitter computed as: tRJIT = SQRT[(tRJIT_OUT)2 – (tRJIT_IN)2].
(6) Parameter is specified by characterization. Not tested in production.

6.10 Timing Diagrams

CDCLVP1204 ai_vo_tr_tf_cas877.gifFigure 1. Output Voltage and Rise/Fall Time
CDCLVP1204 ai_vo_skew_cas886.gif
1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1, 2....11), or as the difference between the fastest and the slowest tPHLn (n = 0, 1, 2....11).
2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn (n = 0, 1, 2....11) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2....11) across multiple devices.
Figure 2. Output and Part-To-Part Skew

6.11 Typical Characteristics

At TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1204 tc_fqcy_diff_vout_swing01_cas880.gif
Figure 3. Differential Output Peak-To-Peak Voltage Vs Frequency
CDCLVP1204 tc_fqcy_diff_vout_swing02_cas880.gif
Figure 4. Differential Output Peak-To-Peak Voltage Vs Frequency