ZHCSPQ4E January   1998  – October 2022 CD54HC540 , CD54HC541 , CD54HCT541 , CD74HC540 , CD74HC541 , CD74HCT540 , CD74HCT541

PRODUCTION DATA  

  1. 特性
  2. 说明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • N|20
  • DW|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

说明

’HC540 和 CD74HCT540 是具有三态输出的反相八路缓冲器和线路驱动器,能够驱动 15 个 LSTTL 负载。’HC541 和 ’HCT541 是具有三态输出的同相八路缓冲器和线路驱动器,能够驱动 15 个 LSTTL 负载。输出使能 (OE1) 和 (OE2) 控制三态输出。如果 OE1OE2 为高电平,则输出处于高阻抗状态。对于数据输出,OE1OE2 都必须为低电平。

封装信息
器件型号 封装(1) 封装尺寸(标称值)
CD74HC540M SOIC (20) 12.80mm × 7.50mm
CD74HC540E PDIP (20) 25.40mm × 6.35mm
CD54HC540F3A CDIP (20) 26.92mm × 6.92mm
CD74HC541M SOIC (20) 12.80mm × 7.50mm
CD74HC541E PDIP (20) 25.40mm × 6.35mm
CD54HC541F CDIP (20) 26.92mm × 6.92mm
CD74HCT540M SOIC (20) 12.80mm × 7.50mm
CD74HCT540E PDIP (20) 25.40mm × 6.35mm
CD74HCT541M SOIC (20) 12.80mm × 7.50mm
CD74HCT541E PDIP (20) 25.40mm × 6.35mm
CD54HCT541F CDIP (20) 26.92mm × 6.92mm
CD74HCT541PW TSSOP (20) 6.50mm × 4.40mm
如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
GUID-20210908-SS0I-JJH3-SHHB-TD4Z9T9M1LR8-low.png功能图