SWRS037B January   2006  – March 2015 CC1150

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
    6. 4.6  RF Transmit
    7. 4.7  Crystal Oscillator
    8. 4.8  Frequency Synthesizer Characteristics
    9. 4.9  Analog Temperature Sensor
    10. 4.10 DC Characteristics
    11. 4.11 Power-On Reset
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
      1. 5.5.1 Chip Status Byte
      2. 5.5.2 Register Access
      3. 5.5.3 SPI Read
      4. 5.5.4 Command Strobes
      5. 5.5.5 FIFO Access
      6. 5.5.6 PATABLE Access
    6. 5.6  Microcontroller Interface and Pin Configuration
      1. 5.6.1 Configuration Interface
      2. 5.6.2 General Control and Status Pins
      3. 5.6.3 Optional Radio Control Feature
    7. 5.7  Data Rate Programming
    8. 5.8  Packet Handling Hardware Support
      1. 5.8.1 Data Whitening
      2. 5.8.2 Packet Format
        1. 5.8.2.1 Arbitrary Length Field Configuration
      3. 5.8.3 Packet Handling in Transmit Mode
      4. 5.8.4 Packet Handling in Firmware
    9. 5.9  Modulation Formats
      1. 5.9.1 Frequency Shift Keying
      2. 5.9.2 Minimum Shift Keying
      3. 5.9.3 Amplitude Modulation
    10. 5.10 Forward Error Correction with Interleaving
      1. 5.10.1 Forward Error Correction (FEC)
      2. 5.10.2 Interleaving
    11. 5.11 Radio Control
      1. 5.11.1 Power On Start-up Sequence
        1. 5.11.1.1 Automatic POR
        2. 5.11.1.2 Manual Reset
      2. 5.11.2 Crystal Control
      3. 5.11.3 Voltage Regulator Control
      4. 5.11.4 Active Mode
      5. 5.11.5 Timing
    12. 5.12 Data FIFO
    13. 5.13 Frequency Programming
    14. 5.14 VCO
      1. 5.14.1 VCO and PLL Self-Calibration
    15. 5.15 Voltage Regulators
    16. 5.16 Output Power Programming
      1. 5.16.1 Shaping and PA Ramping
    17. 5.17 General Purpose and Test Output Control Pins
    18. 5.18 Asynchronous and Synchronous Serial Operation
      1. 5.18.1 Asynchronous Serial Operation
      2. 5.18.2 Synchronous Serial Operation
    19. 5.19 System Considerations and Guidelines
      1. 5.19.1 SRD Regulations
      2. 5.19.2 Frequency Hopping and Multi-Channel Systems
      3. 5.19.3 Wideband Modulation Not Using Spread Spectrum
      4. 5.19.4 Data Burst Transmissions
      5. 5.19.5 Continuous Transmissions
      6. 5.19.6 Low-Cost Systems
      7. 5.19.7 Battery-Operated Systems
      8. 5.19.8 Increasing Output Power
    20. 5.20 Memory
      1. 5.20.1 Configuration Register Details
      2. 5.20.2 Status Register Details
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Bias Resistor
      2. 6.2.2 Balun and RF Matching
      3. 6.2.3 Crystal
      4. 6.2.4 Reference Signal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling
    3. 6.3 PCB Layout Recommendations
      1. 6.3.1 Package Description (QLP 16)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

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5 Detailed Description

5.1 Overview

The CC1150 transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling and data buffering.

5.2 Functional Block Diagram

CC1150 cc1150_sbd_swrs037.gifFigure 5-1 CC1150 Simplified Block Diagram

5.3 Configuration Overview

CC1150 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

  • Power-down and power-up mode
  • Crystal oscillator power up and power down
  • Transmit mode
  • RF channel selection
  • Data rate
  • Modulation format
  • RF output power
  • Data buffering with 64-byte transmit FIFO
  • Packet radio hardware support
  • Forward Error Correction with interleaving
  • Data Whitening

Details of each configuration register can be found in Section 5.20.

Figure 5-2 shows a simplified state diagram that explains the main CC1150 states, together with typical usage and current consumption. For detailed information on controlling the CC1150 state machine, and a complete state diagram, see Section 5.11.

CC1150 simp_state_diag_usage_consump_swrs037.gifFigure 5-2 Simplified State Diagram with Typical Usage and Current Consumption

5.4 Configuration Software

CC1150 can be configured using the SmartRF Studio [11]‎ software. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF Studio user interface for CC1150 is shown in Figure 5-3.

After chip reset, all the registers have default values as shown in the tables in Section 5.20. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

CC1150 smartRF_studio_IF_swrs037.gifFigure 5-3 SmartRF Studio User Interface

5.5 4-wire Serial Configuration and Data Interface

CC1150 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where CC1150 is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address.

During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 5-4 with reference to Table 5-1.

When CSn is pulled low, the MCU must wait until the CC1150 SO pin goes low before starting to transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.

CC1150 config_reg_write_read_swrs037.gifFigure 5-4 Configuration Registers Write and Read Operations

Table 5-1 SPI Interface Timing Requirements

PARAMETER DESCRIPTION MIN MAX UNIT
fSCLK SCLK frequency 10 MHz
100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).
SCLK frequency, single access 9
No delay between address and data byte
SCLK frequency, burst access 6.5
No delay between address and data byte, or between data bytes
tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 µs
tsp CSn low to positive edge on SCLK, in active mode 20 ns
tch Clock high 50 ns
tcl Clock low 50 ns
trise Clock rise time 5 ns
tfall Clock fall time 5 ns
tsd Setup data (negative SCLK edge) to positive edge on SCLK Single access 55 ns
(tsd applies between address and data bytes, and between data bytes) Burst access 76 ns
thd Hold data after positive edge on SCLK 20 ns
tns Negative edge on SCLK to CSn high 20 ns

NOTE

The minimum tsp,pd figure in Table 5-1 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 μs in Table 5-1 is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.

5.5.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

The last four bits (3:0) in the status byte con-tains FIFO_BYTES_AVAILABLE. This field contains the number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are free. Table 5-2 gives a status byte summary.

Table 5-2 Status Byte Summary

BITS NAME DESCRIPTION
7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface.
6:04 STATE[2:0] Indicates the current main state machine mode.
The binary number is the value, the result is the state, and the definition is the current main state machine mode.

000 = Idle : IDLE state(1)
001 = Not used : Not used
010 = TX : Transmit mode
011 = FSTXON : Fast TX ready
100 = CALIBRATE : Frequency synthesizer calibration is running
101 = SETTLING : PLL is settling
110 = Not used : Not used
111 = TXFIFO_UNDERFLOW : TX FIFO has underflowed. Acknowledge with SFTX

3:00 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO.
(1) Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error.

5.5.2 Register Access

The configuration registers on the CC1150 are located on SPI addresses from 0x00 to 0x2E. Table 5-12 lists all configuration registers. The detailed description of each register is found in Section 5.20.

All configuration registers can be both written and read. The read/write bit controls if the register should be written or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x30 through 0x3D, the burst bit is used to select between status registers (burst bit is 1) and command strobes (burst bit is 0). See more in Section 5.5.3. Because of this, burst access is not available for status registers, so they must be read one at a time. The status registers can only be read.

5.5.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (for example, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1150 Errata Notes[8]‎ for more details.

5.5.4 Command Strobes

Command Strobes may be viewed as single byte instructions to CC1150. By addressing a Command Strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, flush the TX FIFO, and so on. The nine command strobes are listed in Table 5-11.

NOTE

An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an SIDLE strobe is issued while the radio is in TX state, any other command strobes issued before the radio reaches IDLE state will be ignored.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to 0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES command strobe is being issued, on will have to wait for the SO pin to go low before the next command strobe can be issued as shown in Figure 5-5.The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.

CC1150 SRES_command_swrs037.gifFigure 5-5 SRES Command Strobe

5.5.5 FIFO Access

The 64-byte TX FIFO is accessed through the 0x3F addresses. When the read/write bit is zero, the TX FIFO is accessed. The TX FIFO is write-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected; hence, CSn can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFO:

  • 0x3F: Single byte access to TX FIFO
  • 0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte (see Section 5.5.1) is output for each new data byte on SO, as shown in Figure 5-5. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO.

NOTE

The status byte contains the number of bytes free before writing the byte in progress to the TX FIFO.

When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a SFTX command strobe. The SFTX command strobe can only be issues in the IDLE or TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.

Figure 5-6 gives a brief overview of different register access types possible.

CC1150 reg_access_types_swrs037.gifFigure 5-6 Register Access Types

5.5.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth.

NOTE

The ASK modulation shaping is limited to output powers below –1 dBm. See SmartRF Studio ‎[11]‎ for recommended shaping sequence.

See also Section 5.16 for details on output-power programming.

The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at zero.

The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero.

NOTE

The content of the PATABLE is lost when entering the SLEEP state. For more information, see DN501[8].

5.6 Microcontroller Interface and Pin Configuration

In a typical system, CC1150 will interface to a microcontroller. This microcontroller must be able to do the following:

  • Program CC1150 into different modes
  • Write buffered data
  • Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn)

5.6.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 5.5.

5.6.2 General Control and Status Pins

The CC1150 has one dedicated configurable pin (GDO0) and one shared pin (GDO1/SO) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 5.17 for more details of the signals that can be programmed. The shared pin is the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.9. With default PTEST register setting (0x7F), the temperature sensor output is only available when the frequency synthesizer is enabled (for example, the MANCAL, FSTXON and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F).

5.6.3 Optional Radio Control Feature

The CC1150 has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, and TX.

This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit.

State changes are commanded as follows:

  • If CSn is high, the SI and SCLK are set to the desired state according to Table 5-3.
  • If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration.

It is only possible to change state with the latter functionality. That means that for instance TX will not be restarted if SI and SCLK are set to TX and CSn toggles. When CSn is low the SI and SCLK has normal SPI functionality.

All pin control command strobes are executed immediately except the SPWD strobe. The SPWD strobe is delayed until CSn goes high.

Table 5-3 Optional Pin Control Coding

CSn SCLK SI FUNCTION
1 X X Chip unaffected by SCLK/SI
0 0 Generates SPWD strobe
0 1 Generates STX strobe
1 0 Generates SIDLE strobe
1 1 Defined on the transceiver version (CC1101)
0 SPI mode SPI mode SPI mode (wakes up into IDLE if in SLEEP/XOFF)

5.7 Data Rate Programming

The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As Equation 1 shows, the programmed data rate depends on the crystal frequency.

Equation 1. CC1150 eq002_r_data_swrs037.gif

The following approach shown in Equation 2 can be used to find suitable values for a given data rate.

Equation 2. CC1150 eq003_drate_e_m_swrs037.gif

If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0.

The data rate can be set from 0.8 kBaud to 500 kBaud with the minimum data rate step size changes according to Table 5-4.

Table 5-4 Data Rate Step Size

MIN DATA RATE
[kBaud]
TYPICAL DATA RATE
[kBaud]
MAX DATA RATE
[kBaud]
DATA RATE STEP SIZE
[kBaud]
0.8 1.2 / 2.4 3.17 0.0062
3.17 4.8 6.35 0.0124
6.35 9.6 12.7 0.0248
12.7 19.6 25.4 0.0496
25.4 38.4 50.8 0.0992
50.8 76.8 101.6 0.1984
101.6 153.6 203.1 0.3967
203.1 250 406.3 0.7935
406.3 500 500 1.5869

5.8 Packet Handling Hardware Support

The CC1150 has built-in hardware support for packet oriented radio protocols.

In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO:

  • A programmable number of preamble bytes.
  • A two byte Synchronization Word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word.
  • Optionally whitening the data with a PN9 sequence.
  • Optionally Interleave and Forward Error Code the data.
  • Optionally compute and add a 2-byte CRC checksum over the data field.

In a system where CC1150 is used as the transmitter and CC1101 as the receiver the recommended setting is 4-byte preamble and 4-byte sync word except for 500 kBaud data rate where the recommended preamble length is 8 bytes.

NOTE

Register fields that control the packet handling features should only be altered when CC1150 is in the IDLE state.

5.8.1 Data Whitening

From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies).

Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver. With CC1150, in combination with a CC1101 at the receiver end, this can be done automatically by setting PKTCTRL0WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted as shown in Figure 5-7. The PN9 sequence is initialized to all ones. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver.

Setting PKTCTRL0.WHITE_DATA=1 is recommended for all uses, except when over-the-air compatibility with other systems is needed.

CC1150 data_white_TXmode_swrs037.gifFigure 5-7 Data Whitening in TX Mode

5.8.2 Packet Format

The format of the data packet can be configured and consists of the following items:

  • Preamble
  • Synchronization word
  • Optional length byte
  • Optional Address byte
  • Payload
  • Optional 2 byte CRC

CC1150 packet_format_swrs037.gifFigure 5-8 Packet Format

The preamble pattern is an alternating sequence of ones and zeros (01010101…). The number of preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLE value. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes.

The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte synch word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice.

C1150 supports both fixed packet length protocols and variable packet length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional automatic CRC.

With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission will continue until turned off manually. The infinite mode can be turned off while a packet is being transmitted. As described in Section 5.8.2.1, this can be used to support packet formats with different length configuration than natively supported by CC1150. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC1150 Errata Notes‎[8] for more details.

NOTE

The minimum packet length supported (excluding the optional length byte and CRC) is one byte of payload data.

5.8.2.1 Arbitrary Length Field Configuration

The packet automation control register, PKTCTRL0, can be reprogrammed during TX. This opens the possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite mode (PKTCTRL0.LENGTH_CONFIG=2) must be active. The PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length and activates fixed length packets. When the internal byte counter reaches the PKTLEN value, the transmission ends (the radio enters the state determined by TXOFF_MODE). Automatic CRC appending can be used (by setting PKTCTRL0.CRC_EN=1).

When, for example, a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure 5-9):

  • Set PKTCTRL0.LENGTH_CONFIG=2.
  • Pre-program the PKTLEN register to mod(600,256)=88.
  • Transmit at least 345 bytes, for example by filling the 64-byte TX FIFO six times (384 bytes transmitted).
  • Set PKTCTRL0.LENGTH_CONFIG=0.
  • The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.

CC1150 arb_length_field_config_swrs037.gifFigure 5-9 Arbitrary Length Field Configuration

5.8.3 Packet Handling in Transmit Mode

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that receives the packet.

The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode.

If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1.

If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by the interleaver, and FEC encoded before being modulated. FEC is enabled by setting MDMCFG1.FEC_EN=1.

5.8.4 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been transmitted. Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be written to the TX FIFO. There are two possible solutions to get the necessary status information:

  1. Interrupt Driven Solution
    • The GDO pins can be used in TX to give an interrupt when a sync word has been transmitted or when a complete packet has been transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that is in the TX FIFO. The IOCFGx.GDOx_CFG=0x02 and the IOCFGx.GDOx_CFG=0x03 configurations are associated with the TX FIFO. See Table 5-10 for more information.
  2. SPI Polling
    • The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The TXBYTES register can be polled at a given rate to get information about the number of bytes in the TX FIFO. Alternatively, the number of bytes in the TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus.
    • It is recommended to employ an interrupt driven solution due to that when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS and TXBYTES is being corrupt. The same is the case when reading the chip status byte. This is explained in the CC1150 Errata Notes‎[8] Refer to the TI website for SW examples ‎[12].

5.9 Modulation Formats

CC1150 supports amplitude, frequency and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register.

Optionally, the data stream can be Manchester coded by the modulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester encoding cuts the effective data rate in half, and thus Manchester is not supported for 500 kBaud. Further note that Manchester encoding is not supported at the same time as using the FEC/Interleaver option or when using MSK modulation.

5.9.1 Frequency Shift Keying

CC1150 has the possibility to use Gaussian shaped 2_FSK (GFSK). The 2-FSK signal is then shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth.

In “true” 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift “softer”, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK.

The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by Equation 3.

Equation 3. CC1150 eq004_fdev_swrs037.gif

The symbol encoding is shown in Table 5-5.

Table 5-5 Symbol Encoding for 2-FSK/GFSK Modulation

FORMAT SYMBOL CODING
2-FSK/GFSK 0 – Deviation
1 + Deviation

5.9.2 Minimum Shift Keying

When using MSK [(Identical to offset QPSK with half-sine shaping (data coding may differ)], the complete transmission (preamble, sync word, and payload) will be MSK modulated.

Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol.

NOTE

When using MSK, Manchester encoding must be disabled by setting MDMCFG2.MANCHESTER_EN=0.

The MSK modulation format implemented in CC1150 inverts the data compared to, for example, signal generators.

5.9.3 Amplitude Modulation

CC1150 supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK).

OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively.

The ASK variant supported by the CC1150 allows programming of the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping will produce a more bandwidth constrained output spectrum.

NOTE

The OOK/ASK pulse shaping feature on the CC1150 does only support output power up to about –1 dBm. The DEVIATN register has no effect when using ASK/OOK.

5.10 Forward Error Correction with Interleaving

5.10.1 Forward Error Correction (FEC)

CC1150 has built in support for Forward Error Correction (FEC) that can be used with CC1101 at the receiver end. To enable this option, set MDMCFG1.FEC_EN to 1. FEC is only supported in fixed packet length mode, that is, when PKTCTRL0.LENGTH_CONFIG=0. FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors.

The use of FEC allows correct reception at a lower Signal-to-Noise RATIO (SNR), thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by Equation 4.

Equation 4. PER = 1 – (1 – BER)packet_length

A lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully.

Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors).

The FEC scheme adopted for CC1150 is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window).

The convolutional coder is a rate 1/2 code with a constraint length of m = 4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. This means that in order to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate.

5.10.2 Interleaving

Data received through real radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart.

CC1150 employs matrix interleaving, which is illustrated in Figure 5-10. The on-chip interleaving buffer is a 4 × 4 matrix. In the transmitter, the data bits are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix and fed to the rate ½ convolutional coder. Conversely, in a CC1101 receiver, the received symbols are written into the rows of the matrix, whereas the data passed onto the convolutional decoder is read from the columns of the matrix.

When FEC and interleaving is used, at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a CC1101.

When FEC and interleaving is used, the minimum data payload is 2 bytes in fixed and variable packet length mode.

CC1150 gen_principle_matrix_swrs037.gifFigure 5-10 : General Principle of Matrix Interleaving

5.11 Radio Control

CC1150 radio_control_state_diag_swrs037.gifFigure 5-11 Radio Control State Diagram

CC1150 has a built-in state machine that is used to switch between different operations states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow.

A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2. The complete radio control state diagram is shown in Figure 5-11. The numbers refer to the state number readable in the MARCSTATE status register. This functionality is primarily for test purposes.

5.11.1 Power On Start-up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described in Section 5.11.1.1 or Section 5.11.1.2, that is, automatic power-on reset or manual reset. After the automatic power-on reset or manual reset it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192, but to optimize performance in TX, an alternative GDO setting should be selected from the settings found in Table 5-10.

5.11.1.1 Automatic POR

A power-on reset circuit is included in the CC1150. The minimum requirements stated in Section ‎4.7 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section ‎10.1 for more details on CHIP_RDYn.

When the CC1150 reset is completed the chip will be in the IDLE state and the crystal oscillator running. If the chip has had sufficient time for the crystal oscillator and voltage regulator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed the SO pin will first go high, indicating that the crystal oscillator and voltage regulator is not stabilized, before going low as shown in Figure 5-12.

CC1150 power_on_reset_swrs037.gifFigure 5-12 Power-on Reset

5.11.1.2 Manual Reset

The other global reset possibility on CC1150 is the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The power-up sequence is as follows (see Figure 5-13):

  • Set SCLK = 1 and SI = 0.
  • Strobe CSn low / high. Make sure to hold CSn high for at least 40 µs relative to pulling CSn low.
  • Pull CSn low and wait for SO to go low (CHIP_RDYn).
  • Issue the SRES strobe on the SI line.
  • When SO goes low again, reset is complete and the chip is in the IDLE state.
CC1150 power_up_sres_swrs037.gifFigure 5-13 Power-up with SRES

NOTE

The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC1150 after this, it is only necessary to issue an SRES command strobe.

It is recommended to always send a SRES command strobe on the SPI interface after power-on even though power-on reset is used.

5.11.2 Crystal Control

The crystal oscillator is automatically turned on when CSn goes low. It will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be used; as described in Section 5.5.1.

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.7.

5.11.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

On the CC1150, all register values (with the exception of the MCSM0.PO_TIMEOUT field) are lost in the SLEEP state. After the chip gets back to the IDLE state, the registers will have default (reset) contents and must be reprogrammed over the SPI interface.

5.11.4 Active Mode

The active transmit mode is activated by the MCU by using the STX command strobe.

The frequency synthesizer must be calibrated regularly. CC1150 has one manual calibration option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting:

  • Calibrate when going from IDLE to TX (or FSTXON)
  • Calibrate when going from TX to IDLE
  • Calibrate every fourth time when going from TX to IDLE

The calibration takes a constant number of XOSC cycles; see Table 5-6 for timing details. When TX is active, the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are:

  • IDLE
  • FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX.
  • TX: Start sending preambles

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. Note that if the radio goes from TX to IDLE by issuing an SIDLE strobe, the automatic calibration-when-going-from-TX-to-IDLE will not be performed.

5.11.5 Timing

The radio controller controls most timing in CC1150, such as synthesizer calibration and PLL lock. Table 5-6 shows timing in crystal clock cycles for key state transitions. Timing from IDLE to TX is constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods. Power on time and XOSC start-up times are variable, but within the limits stated in Section 4.7.

NOTE

In a frequency hopping spread spectrum or a multi-channel protocol, the calibration time can be reduced from 721 µs to approximately 150 µs. This is explained in Section 5.19.2.

Table 5-6 State Transition Timing

DESCRIPTION XOSC PERIODS 26 MHz CRYSTAL
Idle to TX/FSTXON, no calibration 2298 88.4 µs
Idle to TX/FSTXON, with calibration ≈ 21037 809 µs
TX to IDLE, no calibration 2 0.1 µs
TX to IDLE, including calibration ≈ 18739 721 µs
Manual calibration ≈ 18739 721 µs

5.12 Data FIFO

The CC1150 contains a 64 byte FIFO for data to be transmitted. The SPI interface is used for writing to the TX FIFO. Section ‎10.5 contains details on the SPI FIFO access. The FIFO controller will detect underflow in the TX FIFO.

When writing to the TX FIFO, it is the responsibility of the MCU to avoid TX FIFO overflow. This will not be detected by the CC1150. A TX FIFO overflow will result in an error in the TX FIFO content.

Table 5-7 FIFO_THR Settings and the Corresponding FIFO Thresholds

FIFO_THR BYTES in TX FIFO
0000 61
0001 57
0010 53
0011 49
0100 45
0101 41
0110 37
0111 33
1000 29
1001 25
1010 21
1011 17
1100 13
1101 9
1110 5
1111 1

The chip status byte that is available on the SO pin while transferring the SPI address contains the fill grade of the TX FIFO. Section 5.5.1 contains more details on this.

The number of bytes in the TX FIFO can also be read from the TXBYTES.NUM_TXBYTES status register.

The 4-bit FIFOTHR.FIFO_THR setting is used to program the FIFO threshold point. Table 5-7 lists the 16 FIFO_THR settings and the corresponding thresholds for the TX FIFO.

CC1150 example_FIFO_threshold_swrs037.gifFigure 5-14 Example of FIFO at Threshold

A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. The flag is used to generate the FIFO status signals that can be viewed on the GDO pins (see Section 5.17).

Figure 5-15 shows the number of bytes in the TX FIFO when the threshold flag toggles, in the case of FIFO_THR=13. Figure 5-15 shows the flag as the FIFO is filled above the threshold, and then drained below.

CC1150 FIFO_THR_13_swrs037.gifFigure 5-15 FIFO_THR=13 versus Number of Bytes in FIFO

5.13 Frequency Programming

The frequency programming in CC1150 is designed to minimize the programming needed in a channel-oriented system.

To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively.

The base or start frequency is set by the 24-bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used.

The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by Equation 5.

Equation 5. CC1150 eq005_fcarrier_swrs037.gif

With a 26-MHz crystal, the maximum channel spacing is 405 kHz. To get, for example, 1-MHz channel spacing on solution is to use 333-kHz channel spacing and select each third channel in CHANNR.CHAN.

If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state.

5.14 VCO

The VCO is completely integrated on-chip.

5.14.1 VCO and PLL Self-Calibration

The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC1150 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 5-6.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with the MCSM0.FS_AUTOCAL register setting.

In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

The calibration values are not maintained in sleep mode. Therefore, the CC1150 must be recalibrated after reprogramming the configuration registers when the chip has been in the SLEEP state.

To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0, 1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. See more information in the CC1150 Errata Notes[8].

For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time.

5.15 Voltage Regulators

CC1150 contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Section 4.1 and Table 3-1 are not exceeded.

Setting the CSn pin low turns on the voltage regulator to the digital core and start the crystal oscillator. The SO pin on the SPI interface must go low before the first positive edge on the SCLK (setup time is s given in Table 5-1).

If the chip is programmed to enter power-down mode (SPWD strobe issued), the power will be turned off after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low.

The voltage regulator for the digital core requires one external decoupling capacitor. The voltage regulator output should only be used for driving the CC1150.

5.16 Output Power Programming

The RF output power level from the device has two levels of programmability, as illustrated in Figure 5-16. Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. In each case, all the PA power settings in the PATABLE from index 0 up to the FREND0.PA_POWER value are used.

The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to zero and then programming the desired output power to index 0 in the PATABLE.

If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively.

Table 5-8 contains recommended PATABLE settings for various output levels and frequency bands. DN012[3] gives complete tables for the different frequency bands. Using PA settings from 0x61 to 0x6F is not recommended. Table 5-9 contains output power and current consumption for default PATABLE setting (0xC6).

PATABLE must be programmed in burst mode if you want to write to other entries than PATABLE[0]. See Section 5.5.6 for PATABLE programming details.

CC1150 PA_POWER_PATABLE_swrs037.gifFigure 5-16 PA_POWER and PATABLE

Table 5-8 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands

OUTPUT
POWER
[dBm]
315 MHz 433 MHz 868 MHz 915 MHz
SETTING CURRENT CONSUMPTION, TYP. [mA] SETTING CURRENT CONSUMPTION, TYP. [mA] SETTING CURRENT CONSUMPTION, TYP. [mA] SETTING CURRENT CONSUMPTION, TYP. [mA]
–30 0x12 9.9 0x03 10.8 0x03 11.2 0x03 11.1
–20 0x0E 10.4 0x0E 11.4 0x0C 11.7 0x0F 11.7
–10 0x26 12.5 0x26 13.3 0x26 13.7 0x34 13.6
–5 0x57 12.2 0x57 12.9 0x57 13.3 0x56 13.3
0 0x60 14.1 0x60 14.6 0x60 15.5 0x50 15.2
3 0x8B 15.8 0x8A 16.5 0x8A 17.4 0x89 17.4
7 0xCC 21.4 0xC8 23 0xCC 24.4 0xC8 24.6
10 0xC4 25.6 0xC2 26.1 0xC3 29.3 0xC0 29.3

Table 5-9 Output Power and Current Consumption for Default PATABLE Setting

DEFAULT
POWER
SETTING
315 MHz 433 MHz 868 MHz 915 MHz
OUTPUT
POWER
[dBm]
CURRENT CONSUMPTION, TYP. [mA] OUTPUT
POWER
[dBm]
CURRENT CONSUMPTION, TYP. [mA] OUTPUT
POWER
[dBm]
CURRENT CONSUMPTION, TYP. [mA] OUTPUT
POWER
[dBm]
CURRENT CONSUMPTION, TYP. [mA]
0xC6 9.3 24.4 8.1 23.9 8.9 27.3 7.7 25.5

5.16.1 Shaping and PA Ramping

With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This counter value is used as an index for a lookup in the power table. Thus, in order to utilize the whole table, FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on the configuration of the PATABLE. Figure 5-17 shows some examples of ASK shaping.

NOTE

The OOK/ASK pulse shaping feature on the CC1150 is only supported for output power levels below –1 dBm.

CC1150 shaping_ASK_signal_swrs037.gifFigure 5-17 Shaping of ASK Signal

5.17 General Purpose and Test Output Control Pins

The two digital output pins GDO0 and GDO1 are general control pins. Their functions are programmed by IOCFG0.GDO0_CFG and IOCFG1.GDO1_CFG respectively. Table 5-10 shows the different signals that can be monitored on the GDO pins. These signals can be used as an interrupt to the MCU.

GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated, which is useful when the SPI interface is shared with other devices.

The default value for GDO0 is a 125 to 146 kHz clock output (XOSC frequency divided by 192). Because the XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running it can change the clock frequency by writing to IOCFG0.GDO0_CFG.

An on-chip analog temperature sensor is enabled by writing the value 128 (0x80h) to the IOCFG0.GDO0_CFG register. The voltage on the GDO0 pin is then proportional to temperature. See Section 4.9 for temperature sensor specifications.

Table 5-10 GDO signal selection(x = 0 or 1)

GDOx_CFG[5:0] DESCRIPTION
0 (0x00) Reserved – defined on the transceiver version (CC1101).
1 (0x01) Reserved – defined on the transceiver version (CC1101).
2 (0x02) Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX FIFO is below the same threshold.
3 (0x03) Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below the TX FIFO threshold.
4 (0x04) Reserved – defined on the transceiver version (CC1101).
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
6 (0x06) Asserts when sync word has been sent, and de-asserts at the end of the packet. In TX the pin will also de-assert if the TX FIFO underflows.
7 (0x07) Reserved – defined on the transceiver version (CC1101).
8 (0x08) Reserved – defined on the transceiver version (CC1101).
9 (0x09) Reserved – defined on the transceiver version (CC1101).
10 (0x0A) Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.
11 (0x0B) Serial Clock. Synchronous to the data in synchronous serial mode.
In TX mode, data is sampled by CC1150 on the rising edge of the serial clock when GDOx_INV=0.
12 (0x0C) Reserved – defined on the transceiver version (CC1101).
13 (0x0D) Reserved – defined on the transceiver version (CC1101).
14 (0x0E) Reserved – defined on the transceiver version (CC1101).
15 (0x0F) Reserved – defined on the transceiver version (CC1101).
16 (0x10) Reserved – used for test.
17 (0x11) Reserved – used for test.
18 (0x12) Reserved – used for test.
19 (0x13) Reserved – used for test.
20 (0x14) Reserved – used for test.
21 (0x15) Reserved – used for test.
22 (0x16) Reserved – defined on the transceiver version (CC1101).
23 (0x17) Reserved – defined on the transceiver version (CC1101).
24 (0x18) Reserved – used for test.
25 (0x19) Reserved – used for test.
26 (0x1A) Reserved – used for test.
27 (0x1B) PA_PD. PA is enabled when 1, in power-down when 0.
28 (0x1C) Reserved – defined on the transceiver version (CC1101).
29 (0x1D) Reserved – defined on the transceiver version (CC1101).
30 (0x1E) Reserved – used for test.
31 (0x1F) Reserved – used for test.
32 (0x20) Reserved – used for test.
33 (0x21) Reserved – used for test.
34 (0x22) Reserved – used for test.
35 (0x23) Reserved – used for test.
36 (0x24) Reserved – defined on the transceiver version (CC1101).
37 (0x25) Reserved – defined on the transceiver version (CC1101).
38 (0x26) Reserved – used for test.
39 (0x27) Reserved – defined on the transceiver version (CC1101).
40 (0x28) Reserved – used for test.
41 (0x29) CHIP_RDYn
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV=1)
48 (0x30) CLK_XOSC/1 See (1)(2)
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36) CLK_XOSC/8
55 (0x37) CLK_XOSC/12
56 (0x38) CLK_XOSC/16
57 (0x39) CLK_XOSC/24
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192
(1) There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
(2) To optimize RF performance, these signals should not be used while the radio is in TX mode.

5.18 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have been included in the CC1150 to provide backward compatibility with previous TI products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller and simplify software development.

5.18.1 Asynchronous Serial Operation

For backward compatibility with systems already using the asynchronous data transfer from other TI products, asynchronous transfer is also included in CC1150.

When asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included in CC1150 will be disabled, such as packet handling hardware, buffering in the FIFO and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver and FEC, and it is not possible to use Manchester encoding. MSK is not supported for asynchronous transfer.

Setting PKTCTRL0.PKT_FORMAT to 3 enables asynchronous transparent (serial) mode. In TX, the GDO0 pin is used for data input (TX data).

The MCU must control start and stop of transmit with the STX and SIDLE strobes.

The CC1150 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate.

5.18.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial operation mode. In this operational mode the data must be NRZ encoded (MDMCFG2.MANCHESTER_EN=0). In synchronous serial operation mode, data is transferred on a two wire serial interface. The CC1150 provides a clock that is used to set up new data on the data input line. Data input (TX data) is the GDO0 pin. This pin will automatically be configured as an input when TX is active. The TX latency is 8 bits.

Preamble and sync word insertion may or may not be active, dependent on the sync mode set by the MDMCFG3.SYNC_MODE.

If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion in software.

If preamble and sync word insertion is left on, all packet handling features and FEC can be used. When using the packet handling features synchronous serial mode, the CC1150 will insert the preamble and sync word and the MCU will only provide the data payload. This is equivalent to the recommended FIFO operation mode.

5.19 System Considerations and Guidelines

5.19.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315-MHz, 433-MHz, 868-MHz or 915-MHz frequency bands. The CC1150 is specifically designed for such use with its 300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz operating ranges. The most important regulations when using the CC1150 in the 315-MHz, 433-MHz, 868-MHz or 915-MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these regulations can be found in AN001 SRD Regulations for Licence Free Transceiver Operation (SWRA090).

NOTE

Compliance with regulations is dependent on complete system performance. It is the end-product manufactor’s responsibility to ensure that the system complies with regulations.

5.19.2 Frequency Hopping and Multi-Channel Systems

The 315-MHz, 433-MHz, 868-MHz or 915-MHz bands are shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading.

CC1150 is highly suited for FHSS or multi-channel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller.

Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC1150. There are 3 ways of obtaining the calibration data from the chip:

  1. Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 µs. The blanking interval between each frequency hop is then approximately 810 µs.
  2. Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. The VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used. The VCO current calibration value and the charge pump current calibration value available in FSCAL2 and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be used for all RF frequencies for these two registers. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that corresponds to the next RF frequency. The PLL turn on time is approximately 90 µs. The blanking interval between each frequency hop is then approximately 90 µs.
  3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4], strobe STX with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 µs to approximately 150 µs. The blanking interval between each frequency hop is then approximately 240 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution (2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary much in order to have a robust solution. Solution (3) gives approximately 570 µs smaller blanking interval than solution (1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio [11]‎ to get the correct settings for a specific frequency before doing a calibration, regardless of which calibration method is being used. It must be noted that the content of the CC1150 is not retained in SLEEP state, and thus it is necessary to write to the TEST0 register, along with other registers, when returning from the SLEEP state and initiating calibrations.

5.19.3 Wideband Modulation Not Using Spread Spectrum

Digital modulation systems under FFC part 15.247 include FSK and GFSK modulation. A maximum peak output power of 1W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band.

Operating at high data rates and frequency deviation the CC1150 is suited for systems targeting compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is needed to increase the output above +10 dBm. Please refer to DN006[5] for further details concerning wideband modulation and CC1150.

5.19.4 Data Burst Transmissions

The high maximum data rate of CC1150 opens up for burst transmissions. A low average data rate link (for example, 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (for example, 500 kBaud) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range.

5.19.5 Continuous Transmissions

In data streaming applications the CC1150 opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate).

5.19.6 Low-Cost Systems

As the CC1150 provides 500-kBaud multi-channel performance without any external filters, a very low cost system can be made. A HC-49 type SMD crystal is used in the CC1150EM reference design (‎see [1] and [2]).

NOTE

The crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used.

5.19.7 Battery-Operated Systems

In low power applications, the SLEEP state should be used when the CC1150 is not active.

5.19.8 Increasing Output Power

In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this.

The power amplifier should be inserted between the antenna and the balun as shown in Figure 5-18.

CC1150 block_diagram_external_power_amp_swrs037.gifFigure 5-18 Block Diagram of CC1150 Usage with External Power Amplifier

5.20 Memory

The configuration of CC1150 is done by programming 8-bit registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio [11]‎ software. Complete descriptions of the registers are given in Section 5.20.1. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

There are 9 Command Strobe Registers, listed in Table 5-11 Accessing these registers will initiate the change of an internal state or mode. There are 29 normal 8-bit Configuration Registers, listed in Table 5-12. Many of these registers are for test purposes only, and need not be written for normal operation of CC1150.

There are also 6 Status registers, which are listed in Table 5-13. These registers, which are read-only, contain information about the status of CC1150.

The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO.

During the address transfer and while writing to a register or the TX FIFO, a status byte is returned. This status byte is described in Table 5-2.

Figure 5-19 summarizes the SPI address space. Registers that are only defined on the CC1101 transceiver are also listed. CC1101 and CC1150 are register compatible, but registers and fields only implemented in the transceiver always contain 0 in CC1150.

The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F.

Table 5-11 Command Strobes

ADDRESS STROBE NAME DESCRIPTION
0x30 SRES Reset chip.
0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
0x32 SXOFF Turn off crystal oscillator.
0x33 SCAL Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
0x35 STX Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
0x36 SIDLE Exit TX and turn off frequency synthesizer.
0x39 SPWD Enter power down mode when CSn goes high.
0x3B SFTX Flush the TX FIFO buffer.
0x3D SNOP No operation. May be used to pad strobe commands to two bytes for simpler software.

Table 5-12 Configuration Registers Overview

ADDRESS ACRONYM REGISTER NAME SECTION
0x01 IOCFG1 GDO1 output pin configuration Table 5-14
0x02 IOCFG0 GDO0 output pin configuration Table 5-15
0x03 FIFOTHR FIFO threshold Table 5-16
0x04 SYNC1 Sync word, high byte Table 5-17
0x05 SYNC0 Sync word, low byte Table 5-18
0x06 PKTLEN Packet length Table 5-19
0x08 PKTCTRL0 Packet automation control Table 5-20
0x09 ADDR Device address Table 5-21
0x0A CHANNR Channel number Table 5-22
0x0D FREQ2 Frequency control word, high byte Table 5-23
0x0E FREQ1 Frequency control word, middle byte Table 5-24
0x0F FREQ0 Frequency control word, low byte Table 5-25
0x10 MDMCFG4 Modulator configuration Table 5-26
0x11 MDMCFG3 Modulator configuration Table 5-27
0x12 MDMCFG2 Modulator configuration Table 5-28
0x13 MDMCFG1 Modulator configuration Table 5-29
0x14 MDMCFG0 Modulator configuration Table 5-30
0x15 DEVIATN Modulator deviation setting Table 5-31
0x17 MCSM1 Main Radio Control State Machine configuration Table 5-32
0x18 MCSM0 Main Radio Control State Machine configuration Table 5-33
0x22 FREND0 Front end TX configuration Table 5-34
0x23 FSCAL3 Frequency synthesizer calibration Table 5-35
0x24 FSCAL2 Frequency synthesizer calibration Table 5-36
0x25 FSCAL1 Frequency synthesizer calibration Table 5-37
0x26 FSCAL0 Frequency synthesizer calibration Table 5-38
0x29 FSTEST Frequency synthesizer calibration control Table 5-39
0x2A PTEST Production test Table 5-40
0x2C TEST2 Various test settings Table 5-41
0x2D TEST1 Various test settings Table 5-42
0x2E TEST0 Various test settings Table 5-43

Table 5-13 Status Registers Overview

ADDRESS ACRONYM REGISTER NAME SECTION
0x30 (0xF0) PARTNUM Part number for CC1150 Table 5-44
0x31 (0xF1) VERSION Current version number Table 5-45
0x35 (0xF5) MARCSTATE Control state machine state Table 5-46
0x38 (0xF8) PKTSTATUS Current GDOx status and packet status Table 5-47
0x39 (0xF9) VCO_VC_DAC Current setting from PLL calibration module Table 5-48
0x3A (0xFA) TXBYTES Underflow and number of bytes in the TX FIFO Table 5-49
CC1150 SPI_address_space_swrs037.gif
Greyed text: not implemented on CC1150 thus only valid for the transceiver version (CC1101)
Figure 5-19 SPI Address Space

5.20.1 Configuration Register Details

Table 5-14 0x01: IOCFG1 – GDO1 Output Pin configuration

BIT FIELD TYPE RESET DESCRIPTION
7 GDO_DS R/W 0x0 Set high (1) or low (0) output drive strength on the GDO pins.
6 GDO1_INV R/W 0x0 Invert output, that is, select active low (1) / high (0).
5:0 GDO1_CFG[5:0] R/W 0x2E Default is tri-state (See Table 5-10).

Table 5-15 0x02: IOCFG0 – GDO0 Output Pin Configuration

BIT FIELD TYPE RESET DESCRIPTION
7 TEMP_SENSOR_ENABLE R/W 0x0 Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor.
6 GDO0_INV R/W 0x0 Invert output, that is, select active low (1) / high (0).
5:0 GDO0_CFG[5:0] R/W 0x3F Default is CLK_XOSC/192 (See Table 5-10).
It is recommended to disable the clock output during initialization in order to optimize RF performance.

Table 5-16 0x03: FIFOTHR – FIFO Threshold

BIT FIELD TYPE RESET DESCRIPTION
7:4 Reserved R/W 0x0 Write 0 for compatibility with possible future extensions.
3:0 FIFO_THR[3:0] R/W 0x07 Set the threshold for the TX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value.
The binary number is the setting and the result (Bytes in TX FIFO) is the next state after finishing packet transmission.

0000 = 61
0001 = 57
0010 = 53
0011 = 49
0100 = 45
0101 = 41
0110 = 37
0111 = 33
1000 = 29
1001 = 25
1010 = 21
1011 = 17
1100 = 13
1101 = 9
1110 = 5
1111 = 1

Table 5-17 0x04: SYNC1 – Sync Word, High Byte

BIT FIELD TYPE RESET DESCRIPTION
7:0 SYNC[15:8] R/W 0xD3 8 MSB of 16-bit sync word.

Table 5-18 0x05: SYNC0 – Sync Word, Low Byte

BIT FIELD TYPE RESET DESCRIPTION
7:0 SYNC[7:0] R/W 0x91 8 LSB of 16-bit sync word.

Table 5-19 0x06: PKTLEN – Packet Length

BIT FIELD TYPE RESET DESCRIPTION
7:0 PACKET_LENGTH R/W 0xFF Indicates the packet length when fixed length packets are enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed.

Table 5-20 0x08: PKTCTRL0 – Packet Automation Control

BIT FIELD TYPE RESET DESCRIPTION
7 R0 Not Used.
6 WHITE_DATA R/W 0x1 Turn data whitening on / off

0: Whitening off
1: Whitening on

5:4 PKT_FORMAT[1:0] R/W 0x0 Format of TX data:
The binary number is the setting and the result is the packet format.

00 = Normal mode, use TX FIFO
01 = Serial Synchronous mode, data in on GDO0
...
10 = Random TX mode; sends random data using PN9 generator. Used for test/debug.
11 = Asynchronous transparent mode. Data in on GDO0

3 R/W 0x0 Not used.
2 CRC_EN R/W 0x1

1: CRC calculation enabled
0: CRC disabled

1:0 LENGTH_CONFIG[1:0] R/W 0x1 Configure the packet length:
The binary number is the setting and the result is the packet length configuration.

00 = Fixed length packets, length configured in PKTLEN register
01 = Variable length packets, packet length configured by the first byte after sync word
10 = Infinite packet length packets
11 = Reserved

Table 5-21 0x09: ADDR – Device Address

BIT FIELD TYPE RESET DESCRIPTION
7:0 DEVICE_ADDRESS [7:0] R/W 0x0 Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF).

Table 5-22 0x0A: CHANNR – Channel Number

BIT FIELD TYPE RESET DESCRIPTION
7:0 CHAN[7:0] R/W 0x0 The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency.

Table 5-23 0x0D: FREQ2 – Frequency Control Word, High Byte

BIT FIELD TYPE RESET DESCRIPTION
7:6 FREQ[23:22] R 0x0 FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26 MHz or higher crystal frequency).
5:0 FREQ[21:16] R/W 0x1E FREQ[23:0] is the base frequency for the frequency synthesiser in increments of
FXOSC / 216.
Equation 6. CC1150 eq006_FREQ2_register_table_swrs037.gif

Table 5-24 0x0E: FREQ1 – Frequency Control Word, Middle Byte

BIT FIELD TYPE RESET DESCRIPTION
7:0 FREQ[15:8] R/W 0xC4 Ref. FREQ2 register.

Table 5-25 0x0F: FREQ0 – Frequency Control Word, Low Byte

BIT FIELD TYPE RESET DESCRIPTION
7:0 FREQ[7:0] R/W 0xEC Ref. FREQ2 register.

Table 5-26 0x10: MDMCFG4 – Modulator Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:4 Reserved R0 0x08 Defined on the transceiver version (CC1101).
3:0 DRATE_E[3:0] R/W 0x0C The exponent of the user specified symbol rate.

Table 5-27 0x11: MDMCFG3 – Modulator Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:0 DRATE_M[7:0] R/W 0x22 The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The resulting data rate is:
Equation 7. CC1150 eq007_MDMCFG0_register_table_swrs037.gif

The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal.

Table 5-28 0x12: MDMCFG2 – Modulator Configuration

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R0 0x0 Defined on the transceiver version (CC1101).
6:4 MOD_FORMAT[2:0] R/W 0x0 The modulation format of the radio signal:
The binary number is the setting and the result is the modulation format.

000 = 2-FSK
001 = GFSK
010 = N/A
011 = ASK/OOK
100 = N/A
101 = N/A
110 = N/A
111 = MSK

The OOK/ASK pulse shaping feature is only supported for output powers up to –1 dBm.

MSK is only supported for data rates above 26 kBaud.

3 MANCHESTER_EN 0 0x0 Enables Manchester encoding/decoding.

0 = Disable
1 = Enable

2:0 SYNC_MODE[2:0] 2 0x2

Combined sync-word qualifier mode.

The values 0 (000) and 4 (100) disables preamble and sync word transmission. The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word transmission. The values 3 (011) and 7 (111) enables repeated sync word transmission.

The binary number is the setting and the result is the Sync-word qualifier mode (for compatibility with the CC1101 transceiver).

000 = No preamble/sync word
001 = 15/16 sync word bits detected
010 = 16/16 sync word bits detected
011 = 30/32 sync word bits detected
100 = No preamble/sync, carrier-sense above threshold
101 = 15/16 + carrier-sense above threshold
110 = 16/16 + carrier-sense above threshold
111 = 30/32 + carrier-sense above threshold

Table 5-29 0x13: MDMCFG1 – Modulator Configuration

BIT FIELD TYPE RESET DESCRIPTION
7 FEC_EN R/W 0x2 Enable Forward Error Correction (FEC) with interleaving for packet payload

0 = Disable
1 = Enable (Only supported for fixed packet length mode, that is, PKTCTRL0.LENGTH_CONFIG=0)



6:4 NUM_PREAMBLE[2:0] R/W 0x2 Sets the minimum number of preamble bytes to be transmitted.
The binary number is the setting and the result is the minimum number of preamble bytes to be transmitted.

000 = 2
001 = 3
010 = 4
011 = 6
100 = 8
101 = 12
110 = 16
111 = 24

3:2 R0 Not Used.
1:0 CHANSPC_E[1:0] R/W 0x2 2 bit exponent of channel spacing.

Table 5-30 0x14: MDMCFG0 – Modulator Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:0 CHANSPC_M[7:0] R/W 0xF8 8-bit mantissa of channel spacing (initial 1 assumed). The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format:
Equation 8. CC1150 eq007_MDMCFG0_register_table_swrs037.gif

The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

Table 5-31 0x15: DEVIATN – Modulator Deviation Setting

BIT FIELD TYPE RESET DESCRIPTION
7 R0 Not Used.
6:4 DEVIATION_E[2:0] R/W 0x4 Deviation exponent.
3 R0 Not Used.
2:0 DEVIATION_M[2:0] R/W 0x7 When MSK modulation is enabled:
Specifies the fraction of symbol period (1/8-8/8) during which a phase change occurs (‘0’: +90deg, ‘1’: –90deg). Refer to the SmartRF Studio [11]‎ software for correct DEVIATN setting when using MSK.
When 2-FSK/GFSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting frequency deviation is given by Equation 9:
Equation 9. CC1150 eq004_fdev_swrs037.gif

The default values give ±47.607 kHz deviation, assuming 26.0 MHz crystal frequency.
When ASK/OOK modulation is enabled:
This setting has no effect.

Table 5-32 0x17: MCSM1 – Main Radio Control State Machine Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:2 Reserved R0 0x0C Defined on the transceiver version (CC1101).
1:0 TXOFF_MODE[1:0] R/W 0x0 Select what should happen when a packet has been sent (TX):
The binary number is the setting and the result is the next state after finishing packet transmission.

00 = IDLE
01 = FSTXON
10 = Stay in TX (start sending preamble)
11 = Do not use, not implemented on CC1150

Table 5-33 0x18: MCSM0 – Main Radio Control State Machine Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:4 FS_AUTOCAL[1:0] R/W 0x0 Automatically calibrate when going to TX, or back to IDLE:
The binary number is the setting and the result is when to perform automatic calibration.

00 = Never (manually calibrate using SCAL strobe)
01 = When going from IDLE to TX (or FSTXON)
10 = When going from TX back to IDLE
11 = Every 4th time when going from TX to IDLE

3:2 PO_TIMEOUT R/W 0x1 Programs the number of times the six-bit ripple counter must expire after XOSC has stabilized before CHP_RDY_N goes low.
The XOSC is off during power-down and if the regulated digital supply voltage has sufficient time to stabilize while waiting for the crystal to be stable, PO_TIMEOUT can be set to 0. For robust operation it is recommended to use PO_TIMEOUT=2.
The binary number is the setting, the result is the expire count, and the definition is the timeout after XOSC start.

00 = 1 : Approx. 2.3 μs – 2.7 μs
01 = 16 : Approx. 37 μs – 43 μs
10 = 64 : Approx. 146 μs – 171 μs
11 = 256 : Approx. 585 μs – 683 μs

Exact timeout depends on crystal frequency.
In order to reduce start up time from the SLEEP state, this field is preserved in powerdown (SLEEP state).
1:0 Reserved R0 Defined on the transceiver version (CC1101)

Table 5-34 0x22: FREND0 – Front End TX Configuration

BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:4 LODIV_BUF_
CURRENT_TX[1:0]
R/W 0x1 Adjusts current TX LO buffer (input to PA). The value to use in register field is given by the SmartRF Studio ‎[11] software.
3 R0 Not Used.
2:0 PA_POWER[2:0] R/W 0x0 Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 8 different PA settings. In ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats.

Table 5-35 0x23: FSCAL3 – Frequency Synthesizer Calibration

BIT FIELD TYPE RESET DESCRIPTION
7:6 FSCAL3[7:6] R/W 0x02 Frequency synthesizer calibration configuration. The value to write in this field before calibration is given by the SmartRF Studio software.
5:4 CHP_CURR_CAL_EN[1:0] R/W 0x02 Disable charge pump calibration stage when 0.
3:0 FSCAL3[3:0] R/W 0x09 Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: I_OUT = I0·2FSCAL3[3:0]/4.
Fast frequency hopping without calibration for each hop can be done by calibrating up front for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Table 5-36 0x24: FSCAL2 – Frequency Synthesizer Calibration

BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5 VCO_CORE_H_EN R/W 0x0 Choose high (1)/ low (0) VCO.
5:0 FSCAL2[5:0] R/W 0x0A Frequency synthesizer calibration result register. VCO current calibration result and override value.
Fast frequency hopping without calibration for each hop can be done by calibrating up front for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Table 5-37 0x25: FSCAL1 – Frequency Synthesizer Calibration

BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:0 FSCAL1[5:0] R/W 0x20 Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning.
Fast frequency hopping without calibration for each hop can be done by calibrating up front for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Table 5-38 0x26: FSCAL0 – Frequency Synthesizer Calibration

BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R0 Not Used.
6:0 FSCAL0[6:0] R/W 0x0D Frequency synthesizer calibration control. The value to use in register field is given by the SmartRF Studio ‎[11] software.

Table 5-39 0x29: FSTEST – Frequency Synthesizer Calibration Control

BIT FIELD TYPE RESET DESCRIPTION
7:0 FSTEST[7:0] R/W 0x57 For test only. Do not write to this register.

Table 5-40 0x2A: PTEST – Production Test

BIT FIELD TYPE RESET DESCRIPTION
7:0 PTEST[7:0] R/W 0x7F Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state. The default 0x7F value should then be written back before leaving the IDLE state. Other use of this register is for test only.

Table 5-41 0x2C: TEST2 – Various Test Settings

BIT FIELD TYPE RESET DESCRIPTION
7:0 TEST2[7:0] R/W The value to use in this register is given by the SmartRF Studio ‎[11] software.

Table 5-42 0x2D: TEST1 – Various Test Settings

BIT FIELD TYPE RESET DESCRIPTION
7:0 TEST1[7:0] R/W 0x21 The value to use in this register is given by the SmartRF Studio ‎[11] software.

Table 5-43 0x2E: TEST0 – Various Test Settings

BIT FIELD TYPE RESET DESCRIPTION
7:2 TEST0[7:2] R/W 0x02 The value to use in this register is given by the SmartRF Studio ‎[11] software.
1 VCO_SEL_CAL_EN R/W 0x1 Enable VCO selection calibration stage when 1. The value to use in this register is given by the SmartRF Studio ‎[11] software.
0 TEST0[0] R/W 0x1 The value to use in this register is given by the SmartRF Studio ‎[11] software.

5.20.2 Status Register Details

Table 5-44 0x30 (0xF0): PARTNUM – Chip ID

BIT FIELD TYPE RESET DESCRIPTION
7:0 PARTNUM[7:0] R 0x02 Chip part number.

Table 5-45 0x31 (0xF1): VERSION – Chip ID

BIT FIELD TYPE RESET DESCRIPTION
7:0 VERSION[7:0] R 0x04 Chip version number.
Subject to change without notice

Table 5-46 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State

BIT FIELD TYPE RESET DESCRIPTION
7:5 Reserved R0
4:0 MARC_STATE[4:0] R Main Radio Control FSM State(1)
The bit enumerations show the value, the state name, and the state(2).

0x00 = SLEEP : SLEEP
0x01 = IDLE : IDLE
0x02 = XOFF : XOFF
0x03 = VCOON_MC : MANCAL
0x04 = REGON_MC : MANCAL
0x05 = MANCAL : MANCAL
0x06 = VCOON : FS_WAKEUP
0x07 = REGON : FS_WAKEUP
0x08 = STARTCAL : CALIBRATE
0x09 = BWBOOST : SETTLING
0x0A = FS_LOCK : SETTLING
0x0B = N/A : N/A
0x0C = ENDCAL : CALIBRATE
0x0D = N/A : N/A
0x0E = N/A : N/A
0x0F = N/A : N/A
0x10 = N/A : N/A
0x11 = N/A : N/A
0x12 = FSTXON : FSTXON
0x13 = TX : TX
0x14 = TX_END : TX
0x15 = N/A : N/A
0x16 = TX_UNDERFLOW : TX_UNDERFLOW

(1) It is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from the SLEEP or XOFF states.
(2) State (see Figure 5-11).

Table 5-47 0x38 (0xF8): PKTSTATUS – Current GDOx Status

BIT FIELD TYPE RESET DESCRIPTION
7:2 Reserved R0 Defined on the transceiver version (CC1101).
1 R0 Not Used.
0 GDO0 R Current GDO0 value. Note: the reading gives the non-inverted value irrespective what IOCFG0.GDO0_INV is programmed to.
It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDO0_CFG = 0x0A.

Table 5-48 0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module

BIT FIELD TYPE RESET DESCRIPTION
7:0 VCO_VC_DAC[7:0] R Status registers for test only.

Table 5-49 0x3A (0xFA): TXBYTES – Underflow and Number of Bytes

BIT FIELD TYPE RESET DESCRIPTION
7 TXFIFO_UNDERFLOW R
6:0 NUM_TXBYTES R Number of bytes in TX FIFO.