ZHCS267A May   2011  – December 2016

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: AC SPI Data Interface
    7. 6.7 Vertical Communications Bus
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog-to-Digital Conversion (ADC)
        1. 7.3.1.1  General Features
        2. 7.3.1.2  3-to-6 Series Cell Configuration
        3. 7.3.1.3  Cell Voltage Measurements
        4. 7.3.1.4  GPAI or VBAT Measurements
          1. 7.3.1.4.1 Converting GPAI Result to Voltage
          2. 7.3.1.4.2 Converting VBAT Result to Voltage
        5. 7.3.1.5  Temperature Measurement
          1. 7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1-, TS2+, and TS2-)
          2. 7.3.1.5.2 Converting TSn Result to Voltage (Ratio)
        6. 7.3.1.6  ADC Band-Gap Voltage Reference
        7. 7.3.1.7  Conversion Control
          1. 7.3.1.7.1 Convert Start
            1. 7.3.1.7.1.1 Hardware Start
            2. 7.3.1.7.1.2 Firmware Start
          2. 7.3.1.7.2 Data Ready
          3. 7.3.1.7.3 ADC Channel Selection
          4. 7.3.1.7.4 Conversion Time Control
          5. 7.3.1.7.5 Automatic Versus Manual Control
        8. 7.3.1.8  Secondary Protection
          1. 7.3.1.8.1 Protector Functionality
            1. 7.3.1.8.1.1 Using the Protector Functions With 3-5 Cells
        9. 7.3.1.9  Cell Overvoltage Fault Detection (COV)
        10. 7.3.1.10 Cell Undervoltage Fault Detection (CUV)
        11. 7.3.1.11 Overtemperature Detection
          1. 7.3.1.11.1 Ratiometric Sensing
          2. 7.3.1.11.2 Thermistor Power
          3. 7.3.1.11.3 Thermistor Input Conditioning
        12. 7.3.1.12 Fault and Alert Behavior
          1. 7.3.1.12.1 Fault Recovery Procedure
        13. 7.3.1.13 Secondary Protector Built-In Self-Test Features
      2. 7.3.2 Cell Balancing
        1. 7.3.2.1 Cell Balance Control Safety Timer
      3. 7.3.3 Other Features and Functions
        1. 7.3.3.1 Internal Voltage Regulators
          1. 7.3.3.1.1 Internal 5-V Analog Supply
          2. 7.3.3.1.2 Internal 5-V Digital Supply
          3. 7.3.3.1.3 Low-Dropout Regulator (REG50)
          4. 7.3.3.1.4 Auxiliary Power Output (AUX)
        2. 7.3.3.2 Undervoltage Lockout and Power-On Reset
          1. 7.3.3.2.1 UVLO
          2. 7.3.3.2.2 Power-On Reset (POR)
          3. 7.3.3.2.3 Reset Command
        3. 7.3.3.3 Thermal Shutdown (TSD)
        4. 7.3.3.4 GPIO
      4. 7.3.4 Communications
        1. 7.3.4.1 SPI Communications - Device to Host
        2. 7.3.4.2 Device-to-Device Vertical Bus (VBUS) Interface
        3. 7.3.4.3 Packet Formats
          1. 7.3.4.3.1 Data Read Packet
          2. 7.3.4.3.2 Data Write Packet
          3. 7.3.4.3.3 Broadcast Writes
          4. 7.3.4.3.4 Communications Packet Structure
          5. 7.3.4.3.5 CRC Algorithm
          6. 7.3.4.3.6 Data Packet Usage Examples
        4. 7.3.4.4 Device Addressing
    4. 7.4 Device Functional Modes
      1. 7.4.1 SLEEP Functionality
        1. 7.4.1.1 SLEEP State Entry (Bit Set)
        2. 7.4.1.2 SLEEP State Exit (Bit Reset)
    5. 7.5 Programming
      1. 7.5.1 Programming the EPROM Configuration Registers
    6. 7.6 Register Maps
      1. 7.6.1 I/O Register Details
      2. 7.6.2 Register Types
        1. 7.6.2.1 Read-Only (Group 1)
        2. 7.6.2.2 Read / Write (Group 2)
        3. 7.6.2.3 Read / Write, Initialized From EPROM (Group3)
        4. 7.6.2.4 Error Checking and Correcting (ECC) EPROM
      3. 7.6.3 Register Details
        1. 7.6.3.1  DEVICE_STATUS Register (0x00)
        2. 7.6.3.2  GPAI (0x01, 0x02) Register
        3. 7.6.3.3  VCELLn Register (0x03…0x0e)
        4. 7.6.3.4  TEMPERATURE1 Register (0x0f, 0x10)
        5. 7.6.3.5  TEMPERATURE2 Register (0x11, 0x12)
        6. 7.6.3.6  ALERT_STATUS Register (0x20)
        7. 7.6.3.7  FAULT_STATUS Register (0x21)
        8. 7.6.3.8  COV_FAULT Register (0x22)
        9. 7.6.3.9  CUV_FAULT Register (0x23)
        10. 7.6.3.10 PARITY_H Register (0x24) [PRESULT_A (R/O)]
        11. 7.6.3.11 PARITY_H Register (0x25) [PRESULT_B (R/O)]
        12. 7.6.3.12 ADC_CONTROL Register (0x30)
        13. 7.6.3.13 IO_CONTROL Register (0x31)
        14. 7.6.3.14 CB_CTRL Register (0x32)
        15. 7.6.3.15 CB_TIME Register (0x33)
        16. 7.6.3.16 ADC_CONVERT Register (0x34)
        17. 7.6.3.17 SHDW_CTRL Register (0x3a)
        18. 7.6.3.18 ADDRESS_CONTROL Register (0x3b)
        19. 7.6.3.19 RESET Register (0x3c)
        20. 7.6.3.20 TEST_SELECT Register (0x3d)
        21. 7.6.3.21 E_EN Register (0x3f)
        22. 7.6.3.22 FUNCTION_CONFIG Register (0x40)
        23. 7.6.3.23 IO_CONFIG Register (0x41)
        24. 7.6.3.24 CONFIG_COV Register (0x42)
        25. 7.6.3.25 CONFIG_COVT Register (0x43)
        26. 7.6.3.26 CONFIG_UV Register (0x44)
        27. 7.6.3.27 CONFIG_CUVT Register (0x45)
        28. 7.6.3.28 CONFIG_OT Register (0x46)
        29. 7.6.3.29 CONFIG_OTT Register (0x47)
        30. 7.6.3.30 USERx Register (0x48-0x4b) (USER1-4)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Anti-Aliasing Filter
      2. 8.1.2 Host SPI Interface Pin States
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

For typical applications, the following guidelines and practices should be followed closely:

  • VREF and AGND pins require a high-quality 10-µF capacitor be connected between them, in very close physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on signal quality.
    • The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced errors. The device tab should also be connected to this point, and is a convenient common VSS location. The internal VREF should not be used externally to the device by user circuits.
  • The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-µF ceramic capacitor.
  • NOTE

    Because the LDODx inputs are pulled to approximately 7 V during programming, programming time MUST be < 50 ms.

  • The bq76PL536A-Q1 has a low-dropout (LDO) regulator provided to power the thermistors and other external circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-µF capacitor is required for stable operation. The output is internally current-limited and is reduced to near zero, if excess current is drawn, causing die temperatures to rise to unacceptable levels. The 2.2-µF output capacitor is required whether REG50 is used in the design or not. REG50 is disabled in SLEEP mode, may be turned off under thermal-shutdown conditions, and therefore should not be used as a pull-up source for terminating device pins where required.
  • The bq76PL536A-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 kΩ–1 MΩ, typical) is required on this pin if used as an input. If the pull-up is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pull-up is recommended in all designs to prevent an unintentional increase in current draw.
  • Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76PL536A-Q1s. This vertical bus (VBUS) is found on the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed. The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76PL536A-Q1s. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the same name, but opposite suffix.
    • All pins operate within the voltages present at the BAT and VSS pins.
    • The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors. Each device imposes an approximately 30-ns delay on the round trip communications speed; that is, from SCLK rise time (an input to all devices) to the SDO pin transition time requires approximately 30 ns per device. The designer must add to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system.
  • When designing the layout, several considerations need to be taken into account.
    • First, in a stacked system, individual ground planes are necessary for proper noise rejection and stability of the circuits.
    • Second, the ground (VSS) reference per circuit block is unique. The most negative connection, per block “CELL0”, is the ground (VSS) reference for each IC. Do not connect ground references from different ICs. Only the ground reference CELL0, of the most southerly IC, is safe to connect non-isolated test equipment grounds.
  • CAUTION

    Be careful as the BAT and VSS pins may be several hundred volts above system ground, depending on their position in the stack.

    NOTE

    North (_N) pins of the top, most-positive device in the stack, should be connected to the BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the lowest, most-negative device in the stack, should be connected to VSS of the device.

The PowerPAD™ package is a thermally enhanced standard-size IC package designed to eliminate the use of bulky heat sinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. See Figure 65.

The PowerPAD™ package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of the IC. This provides an extremely low-thermal resistance (RθJC) path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heat sink. In addition, through the use of thermal bias, the thermal pad can be directly connected to a ground plane or special heat sink structure designed into the PCB.

bq76PL536A-Q1 powerpad.gif Figure 65. Section View of PowerPAD™ Package and Top View of Solder Mask and Pad

Layout Example

bq76PL536A-Q1 layout.gif Figure 66. Layout