ZHCSCE2I October   2013  – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Versions
    2. 6.2 BQ76920 Pin Diagram
    3. 6.3 BQ76930 Pin Diagram
    4. 6.4 BQ76940 Pin Diagram
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Subsystems
        1. 8.3.1.1 Measurement Subsystem Overview
          1. 8.3.1.1.1 Data Transfer to the Host Controller
          2. 8.3.1.1.2 14-Bit ADC
            1. 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
          3. 8.3.1.1.3 16-Bit CC
          4. 8.3.1.1.4 External Thermistor
          5. 8.3.1.1.5 Die Temperature Monitor
          6. 8.3.1.1.6 16-Bit Pack Voltage
          7. 8.3.1.1.7 System Scheduler
        2. 8.3.1.2 Protection Subsystem
          1. 8.3.1.2.1 Integrated Hardware Protections
          2. 8.3.1.2.2 Reduced Test Time
        3. 8.3.1.3 Control Subsystem
          1. 8.3.1.3.1 FET Driving (CHG AND DSG)
            1. 8.3.1.3.1.1 High-Side FET Driving
          2. 8.3.1.3.2 Load Detection
          3. 8.3.1.3.3 Cell Balancing
          4. 8.3.1.3.4 Alert
          5. 8.3.1.3.5 Output LDO
        4. 8.3.1.4 Communications Subsystem
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 SHIP Mode
    5. 8.5 Register Maps
      1. 8.5.1 Register Details
      2. 8.5.2 Read-Only Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Timing
      2. 9.1.2 Random Cell Connection
      3. 9.1.3 Power Pin Diodes
      4. 9.1.4 Alert Pin
      5. 9.1.5 Sense Inputs
      6. 9.1.6 TSn Pins
      7. 9.1.7 Unused Pins
      8. 9.1.8 Configuring Alternative Cell Counts
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
8.3.1.3.4 Alert

The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host microcontroller. This signal is an OR of all bits in the SYS_STAT register.

In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a “1” to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared.

The ALERT pin may also be driven by an external source; for example, the pack may include a secondary overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will recognize this as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling of both CHG and DSG FET drivers. The device cannot recognize the ALERT signal input high when it is already forcing the ALERT signal high from another condition.

The ALERT pin has no internal debounce support so care should be taken to protect the pin from noise or other parasitic transients.

Note:

It is highly recommended to place an external 500 kΩ–1 MΩ pull-down resistor from ALERT to VSS as close to the IC as possible. Additional recommendations are:

a) To keep all traces between the IC and components connected to the ALERT pin very short.

b) To include a guard ring around the components connected to the ALERT pin and the pin itself.