ZHCSG63C December   2013  – July 2018

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     无线电源联盟（WPC 或者 Qi）感应式充电系统
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 A Brief Description of the Wireless System
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Details of a Qi Wireless Power System and bq51003 Power Transfer Flow Diagrams
      2. 8.3.2  Dynamic Rectifier Control
      3. 8.3.3  Dynamic Efficiency Scaling
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Input Overvoltage
      6. 8.3.6  Adapter Enable Functionality and EN1/EN2 Control
      7. 8.3.7  End Power Transfer Packet (WPC Header 0x02)
      8. 8.3.8  Status Outputs
      9. 8.3.9  WPC Communication Scheme
      10. 8.3.10 Communication Modulator
      11. 8.3.11 Adaptive Communication Limit
      12. 8.3.12 Synchronous Rectification
      13. 8.3.13 Temperature Sense Resistor Network (TS)
      14. 8.3.14 3-State Driver Recommendations for the TS-CTRL Pin
      15. 8.3.15 Thermal Protection
      16. 8.3.16 WPC v1.2 Compliance – Foreign Object Detection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 bq51003 Wireless Power Receiver Used as a Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Using the bq51003 as a Wireless Power Supply
          2. 9.2.1.2.2 Series and Parallel Resonant Capacitor Selection
          3. 9.2.1.2.3 COMM, CLAMP, and BOOT Capacitors
          4. 9.2.1.2.4 Control Pins and CHG
          5. 9.2.1.2.5 Current Limit and FOD
          6. 9.2.1.2.6 RECT and OUT Capacitance
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual Power Path: Wireless Power and DC Input
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.9 WPC Communication Scheme

The WPC communication uses a modulation technique termed backscatter modulation where the receiver coil is dynamically loaded to provide amplitude modulation of the transmitter's coil voltage and current. This scheme is possible due to the fundamental behavior between two loosely coupled inductors (that is, between the Tx and Rx coil). This type of modulation can be accomplished by switching in and out a resistor at the output of the rectifier, or by switching in and out a capacitor across the AC1/AC2 net. Figure 20 shows how to implement resistive modulation.

bq51003 Resistive_mod.gifFigure 20. Resistive Modulation

Figure 21 shows how to implement capacitive modulation.

bq51003 Capacitive_mod.gifFigure 21. Capacitive Modulation

The amplitude change in Tx coil voltage or current can be detected by the transmitters decoder. Figure 22 shows the resulting signal observed by the Tx.

bq51003 Tx_Coil_lusbc8.gifFigure 22. TX Coil Voltage and Current

The WPC protocol uses a differential biphase encoding scheme to modulate the data bits onto the Tx coil voltage and current. Each data bit is aligned at a full period of 0.5 ms (tCLK) or 2 kHz. An encoded ONE results in two transitions during the bit period and an encoded ZERO results in a single transition. See Figure 23 for an example of the differential biphase encoding.

bq51003 bi_phase_encoding_lusay6.gifFigure 23. Differential Biphase Encoding Scheme (WPC Volume 1: Low Power, Part 1 Interface Definition)

The bits are sent LSB first and use an 11-bit asynchronous serial format for each portion of the packet. This includes one start bit, n-data bytes, a parity bit, and a single stop bit. The start bit is always ZERO and the parity bit is odd. The stop bit is always ONE. Figure 24 shows the details of the asynchronous serial format.

bq51003 asynchronour_serial_format_lusay6.gifFigure 24. Asynchronous Serial Formatting (WPC volume 1: Low Power, Part 1 Interface Definition)

Each packet format is organized as shown in Figure 25.

bq51003 packet_format_lusay6.gifFigure 25. Packet Format (WPC Volume 1: Low Power, Part 1 Interface Definition)

Figure 16 shows an example waveform of the receiver sending a rectified power packet (header 0x04).