SLUS928B March   2009  – July 2016

 

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      System Partitioning Diagram
  4. 4Revision History
  5. 5Pin Configuration and Functions
    1.     Pin Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7Detailed Description
    1. 7.1 Feature Description
      1. 7.1.1  Battery Parameter Measurements
        1. 7.1.1.1 Charge and Discharge Counting
        2. 7.1.1.2 Voltage
        3. 7.1.1.3 Voltage Calibration and Accuracy
        4. 7.1.1.4 Current
        5. 7.1.1.5 Auto Calibration
        6. 7.1.1.6 Temperature
      2. 7.1.2  Primary (1st Level) Safety Features
      3. 7.1.3  Secondary (2nd Level) Safety Features
      4. 7.1.4  Charge Control Features
      5. 7.1.5  Gas Gauging
      6. 7.1.6  Lifetime Data Logging Features
      7. 7.1.7  Authentication
      8. 7.1.8  Configuration
        1. 7.1.8.1 System Present Operation
        2. 7.1.8.2 2-, 3-, or 4-Cell Configuration
        3. 7.1.8.3 Cell Balance Control
      9. 7.1.9  Communications
        1. 7.1.9.1 SMBus On and Off State
      10. 7.1.10 SBS Commands
    2. 7.2 Device Functional Modes
      1. 7.2.1 Power Modes
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to 85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
GENERAL PURPOSE I/O
VIH High-level input voltage /PRES, SMBD, SMBC, TS1, TS2 2 V
VIL Low-level input voltage /PRES, SMBD, SMBC, TS1, TS2 0.8 V
VOH Output voltage high /PRES, SMBD, SMBC, TS1, TS2, IL = –0.5 mA VREG27–0.5 V
VOH(FUSE) High level fuse output VBAT = 3.8 V to 9 V, CL = 1 nF 3 VBAT–0.3 8.6 V
VBAT = 9 V to 25 V, CL = 1nF 7.5 8 9
tR(FUSE) FUSE output rise time CL = 1 nF,
VOH(FUSE) = 0 V to 5 V		 10 μs
ZO(FUSE) FUSE output impedance 2 6 kΩ
VFUSE_DET FUSE detect input voltage 0.8 2 3.2 V
VOL Low-level output voltage /PRES, SMBD, SMBC, TS1, TS2, IL = 7 mA 0.4 V
CIN Input capacitance 5 pF
Ilkg Input leakage current /PRES, SMBD, SMBC, TS1, TS2
SMBD and SMBC pull-down disabled		 1 μA
RPD(SMBx) SMBD and SMBC pull-down TA = –40°C to 100°C 600 950 1300 kΩ
RPAD Pad resistance TS1, TS2 87 110 Ω
SUPPLY CURRENT
ICC Normal mode Firmware running, no flash writes 441 μA
ISLEEP Sleep mode Discharge FET ON, Charge FET ON ([NR]=1, [NRCHG]=1) 69 μA
Discharge FET ON, Charge FET OFF ([NR]=1, [NRCHG]=0) 66
Discharge FET OFF, Charge FET OFF ([NR]=0, System not present) 61
ISHUTDOWN Shutdown mode TA = –40°C to 110°C 0.5 1 μA
REG27 POWER ON RESET
VREG27IT– Negative-going voltage input At REG27 2.22 2.35 2.34 V
VREG27IT+ Positive-going voltage input At REG27 2.25 2.5 2.6 V
INTERNAL LDO
VREG Regulator output voltage IREG27 = 10 mA; TA = –40°C to 85°C 2.5 2.7 2.75 V
ΔV(REGTEMP) Regulator output change with temperature IREG = 10 mA; TA = –40°C to 85°C ±0.5%
ΔV(REGLINE) Line regulation IREG = 10 mA ±2 ±4 mV
ΔV(REGLOAD) Load regulation IREG = 0.2 to 10 mA ±20 ±40 mV
I(REGMAX) Current limit 25 50 mA
SRx WAKE FROM SLEEP
VWAKE_ACR Accuracy of VWAKE VWAKE = 1.2 mV 0.2 1.2 2 mV
VWAKE = 2.4 mV 0.4 2.4 3.6
VWAKE = 5 mV 2 5 6.8
VWAKE = 10 mV 5.3 10 13
VWAKE_TCO Temperature drift of VWAKE accuracy 0.5 %/°C
tWAKE Time from application of current and wake of bq3060 0.2 1 ms
COULOMB COUNTER
Input voltage range –0.20 0.25 V
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 Bits
Integral nonlinearity TA = –25°C to 85°C ±0.007 ±0.034 %FSR
Offset error (1) TA = –25°C to 85°C 10 μV
Offset error drift 0.3 0.5 μV/°C
Full-scale error(2) –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input resistance 2.5 MΩ
ADC
Input voltage range –0.2 0.8×VREG27 V
Conversion time 31.5 ms
Resolution (no missing codes) 16 Bits
Effective resolution 14 15 Bits
Integral nonlinearity ±0.020 %FSR
Offset error (3) 70 160 μV
Offset error drift 1 μV/°C
Full-scale error VIN = 1 V –0.8% ±0.2% 0.4%
Full –scale error drift 150 PPM/°C
Effective input resistance 8 MΩ
EXTERNAL CELL BALANCE DRIVE
RBAL_drive Internal pull-down resistance for external cell balance Cell balance ON for VC1, VCi-VCi+1 = 4 V, where i = 1~4 5.7 kΩ
Cell balance ON for VC2, VCi-VCi+1 = 4 V, where = i = 1~4 3.7
Cell balance ON for VC3, VCi-VCi+1 = 4 V, where = i = 1~4 1.75
Cell balance ON for VC4, VCi-VCi+1 = 4 V, where = i = 1~4 0.85
CELL VOLTAGE MONITOR
CELL Voltage Measurement Accuracy(4) TA = –10°C to 60°C ±10 ±20 mV
TA = –40°C to 85°C ±10 ±35
INTERNAL TEMPERATURE SENSOR
T(TEMP) Temperature sensor accuracy ±3% °C
THERMISTOR MEASUREMENT SUPPORT
RERR Internal resistor drift –230 ppm/°C
R Internal resistor TS1, TS2 17 20 kΩ
INTERNAL THERMAL SHUTDOWN(5)
TMAX Maximum REG27 temperature 125 175 °C
TRECOVER Recovery hysteresis temperature 10 °C
HIGH FREQUENCY OSCILLATOR
f(OSC) Operating frequency of CPU clock 2.097 MHz
f(EIO) Frequency error(6) TA = –20°C to 70°C –2% ±0.25% 2%
TA = –40°C to 85°C –3% ±0.25% 3%
t(SXO) Start-up time(7) TA = –25°C to 85°C 3 6 ms
LOW FREQUENCY OSCILLATOR
f(LOSC) Operating frequency 32.768 MHz
f(LEIO) Frequency error(6) TA = –20°C to 70°C –1.5% ±0.25% 1.5%
TA = –40°C to 85°C –2.5% ±0.25% 2.5%
t(LSXO) Start-up time(8) TA = –25°C to 85°C 100 ms
FLASH(9)
Data retention 10 Years
Flash programming write-cycles 20k Cycles
t(ROWPROG) Row programming time 2 ms
t(MASSERASE) Mass-erase time 250 ms
t(PAGEERASE) Page-erase time 25 ms
ICC(PROG) Flash-write supply current 4 6 mA
ICC(ERASE) Flash-erase supply current TA = –40°C to 0°C 8 22 mA
TA = 0°C to 85°C 3 15
RAM BACKUP
I(RBI) RBI data-retention input current VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA = 70°C to 110°C 20 1500 nA
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA = –40°C to 70°C 500
V(RBI) RBI data-retention voltage(9) 1 V
CURRENT PROTECTION THRESHOLDS
V(OCD) OCD detection threshold voltage range, typical RSNS = 0; RSNS is set in STATE_CTL register 50 200 mV
RSNS = 1; RSNS is set in STATE_CTL register 25 100
ΔV(OCDT) OCD detection threshold voltage program step RSNS = 0; RSNS is set in STATE_CTL register 10 mV
RSNS = 1; RSNS is set in STATE_CTL register 5
V(SCCT) SCC detection threshold voltage range, typical RSNS = 0; RSNS is set in STATE_CTL register –100 –300 mV
RSNS = 1; RSNS is set in STATE_CTL register –50 –225
ΔV(SCCT) SCC detection threshold voltage program step RSNS = 0; RSNS is set in STATE_CTL register –50 mV
RSNS = 1; RSNS is set in STATE_CTL register –25
V(SCDT) SCD detection threshold voltage range, typical RSNS = 0; RSNS is set in STATE_CTL register 100 450 mV
RSNS = 1; RSNS is set in STATE_CTL register 50 225
ΔV(SCDT) SCD detection threshold voltage program step RSNS = 0; RSNS is set in STATE_CTL register 50 mV
RSNS = 1; RSNS is set in STATE_CTL register 25
V(OFFSET) SCD, SCC and OCD offset –10 10 mV
V(Scale_Err) SCD, SCC and OCD scale error –10% 10%
CURRENT PROTECTION TIMING
t(OCDD) Overcurrent in discharge delay 1 31 ms
t(OCDD_STEP) OCDD step options 2 ms
t(SCDD) Short circuit in discharge delay AFE.STATE_CNTL[SCDDx2] = 0 0 915 µs
AFE.STATE_CNTL[SCDDx2] = 1 0 1830
t(SCDD_STEP) SCDD step options AFE.STATE_CNTL[SCDDx2] = 0 61 µs
AFE.STATE_CNTL[SCDDx2] = 1 122
t(SCCD) Short circuit in charge delay 0 915 µs
t(SCCD_STEP) SCCD step options 61 µs
t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C		 35 160 µs
tACC Overcurrent and short circuit delay time accuracy Accuracy of typical delay time with WDI active –20% 20%
Accuracy of typical delay time with no WDI input –50% 50%
P-CH FET DRIVE
VO(FETON) Output voltage, charge and discharge FETs on VO(FETONDSG) = V(BAT)–V(DSG), RGS = 1MΩ,
TA = –40°C to 110°C, BAT = 20 V(10) 		12 15 18 V
VO(FETONCHG) = V(PACK)–V(CHG), RGS =1MΩ,
TA = –40°C to 110°C, PACK = 20 V(10) 		12 15 18
VO(FETOFF) Output voltage, charge and discharge FETs off VO(FETOFFDSG) = V(BAT)–V(DSG),
TA = –40°C to 110°C, BAT = 16 V		 0.2 V
VO(FETOFFCHG) = V(PACK)–V(CHG),
TA = –40°C to 110°C, PACK = 16 V		 0.2
tr Rise time CL = 4700 pF; VDSG: 10% to 90% 70 200 µs
CL = 4700 pF; VCHG: 10% to 90% 70 200
tf Fall time CL = 4700 pF; VDSG: 10% to 90% 70 200 µs
CL = 4700 pF; VCHG: 10% to 90% 70 200
PRE-CHARGE/ZVCHG FET DRIVE
V(PreCHGON) VO(PreCHGON) = V(PACK)–V(ZVCHG), pre-charge FET on(11) RGS =1 MΩ, TA = –40°C to 110°C 12 15 18 V
V(PreCHGOFF) Output voltage, pre-charge FET off(11) RGS =1 MΩ, TA = –40°C to 110°C VBAT–0.5 V
tr Rise time CL = 4700 pF, RG = 5.1 kΩ, VZVCHG: 10% to 90% 80 200 µs
tf Fall time CL = 4700 pF, RG = 5.1 kΩ, VZVCHG : 90% to 10% 1.7 ms
SMBus
fSMB SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz
fMAS SMBus master clock frequency Master mode, no clock low slave extend 51.2 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD:STA Hold time after (repeated) start 4 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4 µs
tHD:DAT Data hold time Receive mode 0 ns
Transmit mode 300
tSU:DAT Data setup time 250 ns
tTIMEOUT Error signal/detect See (12) 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period See (13) 4 50 µs
tLOW:SEXT Cumulative clock low slave extend time See (14) 10 ms
tLOW:MEXT Cumulative clock low master extend time See (15) 300 ns
tF Clock/data fall time See (16) 300 ns
tR Clock/data rise time See (17) 1000 ns
SMBus XL
fSMBXL SMBus XL operating frequency Slave mode 40 400 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD:STA Hold time after (repeated) start 4 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4 µs
tTIMEOUT Error signal/detect See (12) 25 35 ms
tLOW Clock low period 1 1 µs
tHIGH Clock high period See (13) 1 2 µs
(1) Post Calibration Performance
(2) Uncalibrated performance. This gain error can be eliminated with external calibration.
(3) Channel to channel offset
(4) This is the performance expected for non-calibrated device.
(5) Parameters assured by design. Not production tested.
(6) The frequency drift is included and measured from the trimmed frequency at VBAT = VPACK = 14.4 V, TA = 25°C
(7) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
(8) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
(9) Specified by design. Not production tested
(10) For a VBAT or VPACK input range of 3.8 V to 25 V, MIN VO(FETON) voltage is 12 V or V(BAT)–1 V, whichever is less.
(11) For a VBAT or VPACK input range of 3.8 V to 25 V, MIN V(PreCHGON) voltage is 12 V or V(BAT)–1V, whichever is less.
(12) The bq3060 times out when any clock low exceeds tTIMEOUT
(13) tHIGH, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 μs causes reset of any transaction involving bq3060 that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then the timeout is disabled.
(14) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(15) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(16) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(17) Fall time tF = 0.9VDD to (VILMAX – 0.15)
bq3060 smbus_tim_lus928.gif
1. SCLKACK is the acknowledge-related clock pulse generated by the master.