ZHCSP94A 数据表 | 德州仪器 TI.com.cn

ZHCSP94A November 2021 – February 2022 BQ27Z746

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YAH|15
- MXBG425

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6.5.3 Battery Protection (CHG, DSG)

Protection hardware circuits operating over free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
N-CH FET DRIVER, CHG AND DSG
V_DRIVER	Gate Driver Voltage, V_CHG or V_DSG	C_LOAD = 8 nF		2 × VDD		V
A_FETON	FET driver gain factor, Vgs voltage to FET	A_FETON = (V_driver – VDD)/VDD, C_LOAD = 8 nF, UVP < VDD < 3.8 V	0.9	1.0	1.2	V/V
V_DSGOFF	DSG FET driver off output voltage	V_DSGOFF = V_DSG – PACK, C_L= 8 nF			0.2	V
V_CHGOFF	CHG FET driver off output voltage	V_CHGOFF = V_CHG – VSS , C_L= 8 nF			0.2	V
t_rise	FET driver rise time ⁽¹⁾	C_L = 8 nF, (Vdriver – VDD)/VDD = 1x V_FETON changes from VDD to 2×VDD		400	800	us
t_fall	FET driver fall time ⁽¹⁾	CL = 8 nF, V_FETON changes from V_FETMAX to V_FETOFF		50	200	us
V_{FET_SHUT}	Firmware FET driver shut down voltage ⁽²⁾⁽⁴⁾	Configurable with 1-mV steps	2000	2100	5000	mV
V_{FET_SHUT_REL}	Firmware FET driver shut down release ⁽²⁾⁽⁴⁾	Configurable with 1-mV steps	2000	2300	5000	mV
I_LOAD	FET driver maximum loading				10	uA
VOLTAGE PROTECTION
V_OVP	Hardware overvoltage protection (OVP) detection range ⁽³⁾	Recommended threshold range. Factory trimmed in 50-mV steps	3500		5000	mV
V_OVP	Factory default trimmed threshold⁽³⁾	Recommended threshold range. Factory trimmed in 50-mV steps		4525		mV
V_{OVP_ACC}	Hardware OVP detection accuracy ⁽³⁾	TA = 25^oC, C_LOAD at CHG/DSG < 1 μA	–15		15	mV
		TA = 0^oC to 60^oC, C_LOAD at CHG/DSG < 1 μA	–25		25	mV
		TA = –40^oC to 85^oC, C_LOAD at CHG/DSG < 1 μA	–50		50	mV
V_{FW_OVP}	Firmware OVP detection range ⁽⁴⁾	Configurable with 1-mV steps	2000	4490	5000	mV
V_{FW_OVP_REL}	Firmware OVP release range ⁽⁴⁾	Configurable with 1-mV steps	2000	4290	5000	mV
V_UVP	Hardware undervoltage (UVP) detection range ⁽³⁾	Recommended threshold range. Factory trimmed in 50-mV steps	2000		4000	mV
V_UVP	Factory default trimmed threshold⁽³⁾	Recommended threshold range. Factory trimmed in 50-mV steps		2300		mV
V_{UVP_ACC}	Hardware UVP detection accuracy ⁽³⁾	TA = 25^oC, C_LOAD at CHG/DSG < 1 μA	–20		20	mV
		TA = 0^oC to 60^oC, C_LOAD at CHG/DSG < 1uA	–30		30	mV
		TA = –40^oC to 85^oC, C_LOAD at CHG/DSG < 1uA	–50		50	mV
V_{FW_UVP}	Firmware UVP detection range ⁽⁴⁾	Configurable with 1 mV steps	2000	2500	5000
V_{FW_UVP_REL}	Firmware UVP release range ⁽⁴⁾	Configurable with 1 mV steps	2000	2900	5000	mV
R_PACK-VSS	Resistance between PACK and VSS	SHUTDOWN mode only	100	300	550	kΩ
V_RCP	Reverse Charge Protection limit	–10V Continuous Operating, –12 V ABS MAX	–10			V
CURRENT PROTECTION
V_OCC	Sense voltage threshold range for Overcurrent in Charge (OCC) ⁽³⁾⁽⁴⁾	Recommended threshold range. Factory trimmed in 1-mV steps	1		100	mV
V_OCC	Factory default trimmed threshold⁽³⁾	Recommended threshold range. Factory trimmed in 1-mV steps		14		mV
V_OCC	OCC 2-mV step design option	2 mV step configuration option	2		256	mV
I_OCC	Effective OCC current threshold range from V_OCC⁽¹⁾⁽⁴⁾	Ideal R_SNS = 1 mΩ	4	14	100	A
		Ideal R_SNS = 2 mΩ	2	7	50
		Ideal R_SNS = 5 mΩ	0.8	2.8	20
I_{FW_OCC}	Firmware OCC detection range ⁽⁴⁾	Configurable with 1 mA steps	0	12000	+I_{CC_IN}	mA
V_OCD	Sense voltage threshold range for Overcurrent in discharge (OCD) ⁽³⁾⁽⁴⁾	Recommended threshold range. Factory trimmed in 1-mV steps	–4		–100	mV
V_OCD	Factory default trimmed threshold⁽³⁾	Recommended threshold range. Factory trimmed in 1-mV steps		–16		mV
V_OCD	OCD 2-mV step design option	±2 mV step configuration option	–2		–256	mV
I_OCD	Effective OCD current threshold range from V_OCD⁽¹⁾⁽⁴⁾	Ideal R_SNS = 1 mΩ	–4	–16	–100	A
		Ideal R_SNS = 2 mΩ	–2	–8	–50
		Ideal R_SNS = 5 mΩ	–0.8	–3.2	–20
I_{FW_OCD}	Firmware OCD detection range ⁽⁴⁾	Configurable with 1-mA steps	–I_{CC_IN}	–7000	₀	mA
V_SCD	Sense voltage threshold range for Short circuit current in discharge (SCD) ⁽³⁾⁽⁴⁾	Threshold factory trimmed with 1-mV steps	–5		–120	mV
V_SCD	Factory default trimmed threshold⁽³⁾	Threshold factory trimmed with 1-mV steps		–20		mV
I_SCD	Effective SCD current threshold range from V_SCD⁽¹⁾⁽⁴⁾	Ideal R_SNS = 1 mΩ	–5	–20	–120	A
		Ideal R_SNS = 2 mΩ	–2.5	–10	–60
		Ideal R_SNS = 5 mΩ	–1	–4	–24
V_{OC_ACC}	Overcurrent (OCC, OCD, SCD) detection accuracy ⁽³⁾	<20 mV, TA = –25°C to 60^oC	-2.1		2.1	mV
		<20 mV	–2.1		2.1
		20 mV–55 mV	–3		3
		56 mV–100 mV	–5		5
		>100 mV	–12		12
I_PACK-VDD	Current sink between PACK and VDD during current fault	Load removal detection in firmware		15		μA
V_{OC_REL}	OCC fault release threshold	(V_PACK – V_BAT)		100		mV
V_{OC_REL}	OCD, SCD fault release threshold	(V_PACK – V_BAT)		–400		mV
OVERTEMPERATURE PROTECTION
T_{OTC_TRIP}	OTC trip/release threshold ⁽²⁾⁽⁴⁾	Firmware-based and configurable in 0.1°C steps	–40.0	55.0	150.0	°C
T_{OTC_REL}	OTC trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	50.0	150.0	°C
T_{OTD_TRIP}	OTD trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	60.0	150.0	°C
T_{OTD_REL}	OTD trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	55.0	150.0	°C
T_{UTC_TRIP}	UTC trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	0.0	150.0	°C
T_{UTC_REL}	UTC trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	5.0	150.0	°C
T_{UTD_TRIP}	UTD trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	0.0	150.0	°C
T_{UTD_REL}	UTD trip/release threshold ⁽²⁾⁽⁴⁾		–40.0	5.0	150.0	°C
PROTECTION DELAY⁽¹⁾
t_OVP	OVP detection delay (debounce) options ⁽¹⁾⁽⁴⁾	Configurable with 4095 delay options in 1.953-ms steps. Factory default = 1000 ms (512 counts) typical	1.953	1000	7998	ms
t_UVP	UVP detection delay (debounce) options ⁽¹⁾⁽⁴⁾	Configurable with 127-delay options in 1.953-ms steps. Factory default = 127 ms (65 counts) typical	1.953	127	248	ms
t_OCD	OCD detection delay (debounce) options ⁽¹⁾⁽⁴⁾	Configurable with 31 delay options in 1.953-ms steps. Factory default = 7.8 ms (4 counts) typical	1.953	7.8	60.5	ms
t_OCC	OCC detection delay (debounce) options ⁽¹⁾⁽⁴⁾	Configurable with 255 delay options in 0.244-ms steps. Factory default = 15.9 ms (65 counts) typical	0.244	15.9	62.3	ms
t_SCD	SCD detection delay (debounce) options ⁽¹⁾⁽⁴⁾	Configurable with seven delay options in 122-µs steps. Factory default = 244-µs (2 counts) typical	122	244	854	µs
T_{OTC_DLY}	OTC trip delay⁽²⁾⁽⁴⁾	Firmware-based and configurable in 1-s steps. The typical value is the data flash factory default.	0	2	255	s
T_{OTD_DLY}	OTD trip delay⁽²⁾⁽⁴⁾		0	2	255	s
T_{UTC_DLY}	UTC trip delay⁽²⁾⁽⁴⁾		0	2	255	s
T_{UTD_DLY}	UTD trip delay⁽²⁾⁽⁴⁾		0	2	255	s
ZERO VOLT (LOW VOLTAGE) CHARGING
V_0CHGR	Charger voltage requires to start zero-volt charging	V_PACK – VSS	1.6			V
V_0INH	Battery voltage that inhibits zero-volt charging	VDD – VSS		1.0	1.1	V

(1) Specified by design. Not production tested.

(2) Firmware-based parameter. Not production tested.

(3) Accuracy assured by factory trim at specified default threshold. A change from the default threshold requires device calibration in the field. Refer to the BQ27Z746 Technical Reference Manual.

(4) Specified typical value is the factory default. Not production tested. The data flash configuration value can be changed in FULL ACCESS mode and is locked in SEALED mode. Refer to the BQ27Z746 Technical Reference Manual.