ZHCSQ82 September   2022 BQ25176M

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power Up from Input Source
        1. 7.3.1.1 ISET Pin Detection
        2. 7.3.1.2 VSET Pin Detection
        3. 7.3.1.3 Charger Power Up
      2. 7.3.2 Battery Charging Features
        1. 7.3.2.1 Lithium-Ion Battery Charging Profile
        2. 7.3.2.2 Input Voltage Based Dynamic Power Management (VINDPM)
        3. 7.3.2.3 Charge Termination and Battery Recharge
      3. 7.3.3 Status Outputs ( PG, STAT)
        1. 7.3.3.1 Power Good Indicator (PG Pin)
        2. 7.3.3.2 Charging Status Indicator (STAT)
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Input Overvoltage Protection (VIN_OV)
        2. 7.3.4.2 Output Overvoltage Protection (VOUT_OVP)
        3. 7.3.4.3 Output Overcurrent Protection (IOUT_OCP)
        4. 7.3.4.4 Thermal Regulation and Thermal Shutdown (TREG and TSHUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown or Undervoltage Lockout (UVLO)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Standby Mode
      4. 7.4.4 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Li-Ion Charger Design Example
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LiFePO4 Charger Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

GUID-20220803-SS0I-GHLP-8T7Z-HCGVGPHFZX4P-low.gifFigure 5-1 DSG Package8-Pin WSONTop View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMENUMBER
IN1PInput power, connected to external DC supply. Bypass IN with at least 1-μF capacitor to GND, placed close to the IC.
ISET2IPrograms the device fast-charge current. External resistor from ISET to GND defines fast charge current value. Expected range is 30 kΩ (10 mA) to 375 Ω (800 mA). ICHG = KISET / RISET. Precharge current is defined as 20% of ICHG. Termination current is defined as 10% of ICHG.

BIAS

3

I

Bias sense pin. Connect an external 10-kΩ resistor from this pin to GND. This pin can also be used as a charging disable pin by pulling the pin to GND by means of an external NMOS. Refer to the applications section for more information.
GND4–Ground pin
STAT5OOpen drain charger status indication output. Connect to pull-up rail via 10-kΩ resistor.
LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When a fault condition is detected STAT pin blinks at 1 Hz.
PG6OOpen drain charge power good indication output. Connect to pull-up rail via 10-kΩ resistor.
PG pulls low when VIN > VIN_LOWV and VOUT + VSLEEPZ < VIN < VIN_OV.
VSET7IPrograms the regulation voltage for OUT pin with a pull-down resistor. Valid resistor range is 18.2 kΩ to 100 kΩ, values outside this range will suspend charge. Refer to Section 7.3.1.2 for voltage level details. Recommend using ±1% tolerance resistor with <200 ppm/ºC temperature coefficient.
OUT8PBattery connection. System Load may be connected in parallel to battery. Bypass OUT with at least 1-μF capacitor to GND, placed close to the IC.
Thermal Pad——Exposed pad beneath the IC for heat dissipation. Solder thermal pad to the board with vias connecting to solid GND plane.