8.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x0]
ICCTRL2 is shown in Figure 51 and described in Table 33.
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Figure 51. ICCTRL2 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
GPO_PG |
RESERVED |
HWRESET_14S_WD |
CHARGER_DISABLE |
R/W-3b000 |
R/W-1b0 |
R/W-2b00 |
R/W-1b0 |
R/W-1b0 |
|
Table 33. ICCTRL2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-5 |
RESERVED |
R/W |
3b000 |
Reserved |
4 |
GPO_PG |
R/W |
1b0 |
/PG General Purpose Output State Control
1b0 = Pulled Down
1b1 = High Z
|
3-2 |
RESERVED |
R/W |
2b00 |
Reserved |
1 |
HWRESET_14S_WD |
R/W |
1b0 |
Enable for 14-second I2C watchdog timer for HW Reset after VIN connection
1b0 = Timer disabled
1b1 = Device will perform HW reset if no I2C transaction is done within 14s after VIN is present
|
0 |
CHARGER_DISABLE |
R/W |
1b0 |
Charge Disable
1b0 = Charge enabled if /CE pin is low
1b1 = Charge disabled
|