ZHCSJD3B July 2018 – February 2019 BQ25150
The device integrates a low Iq load switch which can also be used as a regulated output. The LDO/LS has a dedicated input pin VINLS and can support up to 150 mA of load current
The LSCTRL may be enabled/disabled through I2C. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to VINLS pin. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times larger than the output capacitor on LS/LDO output.
The output voltage is programmable using the LS_LDO bits in the registers. The LS_LDO output can only be changed when the EN_LS_LDO or LSCTRL pin have disabled the output. The LS/LDO voltage is calculated using the following equation: VLSLDO = 0.6 V + LS_LDOCODE × 100 mV up to 3.7 V. All higher codes will set the output to 3.7V.
|I2C EN_LS_LDO||LS_CONFIG||LS/LDO OUTPUT|
The current capability of the LDO will depend on the VINLS input voltage and the programmed output voltage. When the LS/LDO output is disabled through the register, an internal pull-down will discharge the output.
The LDO has output current limit protection, limiting the output current in the event of a short in the output. When the LDO output current limit trips and is active for at least 1ms, the device will set a flag and send an interrupt to the host. The LDO may be set to operate as a load switch by setting the LS_SWITCH_CONFG bit. Note that in order to change the configuration the LDO must be disabled first, then the LS_SWITCH_CONFG bit is set for it to take effect.