SLVSKM8 January   2026 BQ24138

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-On-Reset (POR)
      2. 6.3.2  Device Power Up from Battery
      3. 6.3.3  Device Power Up from Input Source
        1. 6.3.3.1 REGN LDO Power Up
        2. 6.3.3.2 Poor Source Qualification
        3. 6.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 6.3.3.4 Converter Power-Up
        5. 6.3.3.5 Input Current Optimizer (ICO)
        6. 6.3.3.6 25
      4. 6.3.4  Power Path Management
        1. 6.3.4.1 Narrow VDC Architecture
        2. 6.3.4.2 Dynamic Power Management
          1. 6.3.4.2.1 Input Current Limit on ILIM Pin
        3. 6.3.4.3 High Impedance (HIZ) Mode
      5. 6.3.5  Battery Charging Management
        1. 6.3.5.1 Autonomous Charging Cycle
        2. 6.3.5.2 Battery Charging Profile
        3. 6.3.5.3 Charging Termination
        4. 6.3.5.4 Thermistor Qualification
          1. 6.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 6.3.5.4.2 TS Pin Thermistor Configuration
          3. 6.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 6.3.5.4.4 JEITA Charge Rate Scaling
          5. 6.3.5.4.5 TS_BIAS Pin
        5. 6.3.5.5 Charging Safety Timers
      6. 6.3.6  USB On-The-Go (OTG)
        1. 6.3.6.1 Boost OTG Mode
      7. 6.3.7  Integrated 12-bit ADC for Monitoring
      8. 6.3.8  Status Outputs (INT , PG , STAT)
        1. 6.3.8.1 PG Pin Power Good Indicator
        2. 6.3.8.2 Charging Status Indicator (STAT)
        3. 6.3.8.3 Interrupt to Host (INT)
      9. 6.3.9  BATFET Control
        1. 6.3.9.1 Shutdown Mode
        2. 6.3.9.2 Ultra-Low Power Mode (ULPM)
        3. 6.3.9.3 System Power Reset
      10. 6.3.10 Protections
        1. 6.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 6.3.10.1.1 Battery Overcurrent Protection
          2. 6.3.10.1.2 Battery Undervoltage Lockout
        2. 6.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 6.3.10.2.1 Input Overvoltage
          2. 6.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 6.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 6.3.10.2.4 System Short
          5. 6.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 6.3.10.2.6 Sleep and Poor Source Comparators
        3. 6.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 6.3.10.3.1 Boost Mode Overvoltage Protection
          2. 6.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 6.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 6.3.10.3.4 Boost Mode Battery Undervoltage
          5. 6.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 6.3.10.3.6 Boost Mode SYS Short
        4. 6.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 6.3.10.4.1 Thermal Protection in Buck Mode
          2. 6.3.10.4.2 Thermal Protection in Boost Mode
          3. 6.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host Mode and Default Mode
      2. 6.4.2 Register Bit Reset
    5. 6.5 Programming
      1. 6.5.1 Serial Interface
        1. 6.5.1.1 Data Validity
        2. 6.5.1.2 START and STOP Conditions
        3. 6.5.1.3 Byte Format
        4. 6.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 6.5.1.5 Target Address and Data Direction Bit
        6. 6.5.1.6 Single Write and Read
        7. 6.5.1.7 Multi-Write and Multi-Read
  8. Register Maps
    1. 7.1 BQ24138 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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Serial Interface

BQ24138 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial data line (SDA), and a serial clock line (SCL).

The device has 7-bit I2C address 0x6B, receiving control inputs from a host device such as a micro-controller or digital signal processor through register addresses defined in the Register Map. The host device initiates all transfers and the charger responds. Register reads outside of these addresses return 0xFF. When the bus is free, both SDA and SCL lines are HIGH.

The I2C interface supports standard mode (up to 100kbits/s), fast mode (up to 400kbits/s) and fast mode plus (up to 1Mbits/s.) These lines are pulled up to a reference voltage using a pullup resistor. The device I2C detection thresholds support a communication reference voltage between 1.2V - 5V.

Due to the ultra low IQ when the device operates in low power mode, verifying a minimum of 90μs between a START command and any subsequent START command on the I2C bus is necessary. The recommended minimum tbuf (bus free time between a STOP and START condition) depends on the I2C mode:

  • Standard mode (100kbits/s):
    • No additional requirements
  • Fast mode (400kbits/s):
    • Increase I2C tbuf to at least 68μs
    • If using repeated start commands, verify I2C tsu:STA is at least 68μs
  • Fast mode plus (1Mbits/s):
    • Increase I2C tbuf to at least 81μs
    • If using repeated start commands, verify I2C tsu:STA is at least 81μs

These recommendations assume a successful I2C transaction. Verify that a minimum 90μs time between two START commands in the case of a NACK.